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I'm facing some weird errors from quartus when I try this.

Here's the code (all the unsigned & other weird functions was my attempt at persuading Quartus to compile it.)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

...
variable data : std_logic_vector(17 downto 0) := "000000000000000011";

...

-- 00000000111111000 original
-- 00000000000011111 shifted
-- 00000000000011000 result (AND)

data := std_logic_vector(unsigned(data) & shift_right(unsigned(data), 4));


-- 00000000011111000 original
-- 00000000111110000 shifted
-- 00000000111111000 result (OR)

data := std_logic_vector(unsigned(data) or shift_left(unsigned(data), 1));

I've left out quite a lot of the code, but the broken parts are left the same.

I'm getting

Error (10344): VHDL expression error at snake_driver.vhd(66): expression has 36 elements, but must have 18 elements

How to do it right?

MightyPork
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1 Answers1

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The & operator is not the same as the and operator in VHDL. You are looking for the and operator to perform a bitwise and operation. & is the concatenation operator on vectors and using it between two 18-bit vectors will produce a 36-bit vector (and likewise a vector width mismatch) as indicated by your error message.

QuantumRipple
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  • Oh that's silly. Okay, this fixed it. And, am I doing it right? I'm not really sure about all the type casting. Is this the easiest method? – MightyPork Nov 07 '14 at 23:49
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    If you're trying to shift or rotate by a constant value, it is often easier to slice and concatenate a std_logic_vector. A simple shift right by 4 would be `data := x"0"&data(17 downto 4);`. A rotate right by 4 would be `data := data(3 downto 0) & data(17 downto 4);` – QuantumRipple Nov 08 '14 at 00:22
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    Alternatively, you could just use `unsigned` as your data type for `data`. You can pretty much treat it just like a std_logic_vector. – QuantumRipple Nov 08 '14 at 00:23
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    +1 for "Alternatively, you could just use unsigned". Any time you are throwing typecasts at a problem, stop and ask if you're fighting the type system instead of using it. Usually they are pointing you at a better design. (but not always!) –  Nov 08 '14 at 11:17