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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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Multiple Interrupt Senders in one peripheral in Qsys

Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated…
Mishka
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Error (10170): expecting "<=", or "=", or "+=", or "-=", or "*=", or "/=", or "%=", or "&=", or "|=", or "^=", etc

module accumulator ( input [7:0] A , input reset, input clk, output reg carryout, output reg overflow, output reg [8:0] S, output reg HEX0, output reg HEX1, output reg HEX2, output reg HEX3 ); reg…
kqs5395
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Generating post-synthesis verilog model in Quartus II

I have Xilinx background and now I happened to write some code on Altera devices. I have a question about generating post-synthesis models (also post-fit). On Xilinx I had netget which was able to generate verilog or vhdl post-synthesis model of my…
mucka
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How to login as "root user" in Altera Embedded Command Shell?

Hello! I am terribly new at Linux and am struggling to login as a "root user". My picture below shows my attempts. What kind of user am I in now? How do I login as a root user? This is the project I'm trying to run right now:
VKkaps
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How to know if a std_logic has changed its value?

I want to know every time a std_logic has changed from 0 to 1 and viceversa. So far I've made this, but the following error shows up: *Error (10819): Netlist error at prueba.vhd(15): can't infer register for b because it changes value on both…
Carlos Ortiz
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Altera Arria V latest software for OpenCL

I recently bought a new Altera Arria V board 1. I am planning to use it to design a certain application using OpenCL. Unfortunately, I didn't find so far the required software to get it work. I mean by that the Altera RTE for OpenCL and the required…
user75
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Simulating INOUT port with Modelsim (VHDL)

Im trying to simulate a RAM memory with Quartus and Modelsim by Altera. The problem is that when i assing values to data_inout in the test bench and simulate, the wave is always in 'U' state. It doesnt take any value when i do data_inout <=…
rockstiff
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C:/altera/15.0/work/ethernet_frame generator.vhd(153): (vcom-1339) Case statement choices cover only 4 out of 81 cases

Modelsim displaysCase statement choices cover only 4 out of 81 cases for my ethernet frame generation code I am getting this error after execution of my very long program in VHDL.It comprises of many case statements and case within case statements…
susa1012
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How can I use HPS pins of altera FPGA development board?

How can I design my own MAC layer function to access Ethernet chip instead of using altera IP function. My board is DE1-SoC with cyclone V 5CSEMA5F31C6 chip. The pins to access Ethernet chip are made to be HPS pins which I can't assign my own…
yanqiangliu
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Calculate fmax of Altera design

After I finished my design compilation on Quartus, I get multiple result for fmax as shown below. I want to know, what does it means? and How can I calculate the fmax of the all design?. My design is implementation for the following equation: for(i…
abdelhamedia
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Visual studio 14.0 LNK2001 (unresolved external symbol ) with OpenCL

I am new to OpenCL. When I tried the examples from the website of Altera, I got several LNK2001 errors as follows Severity Code Description Project File Line Error LNK2001 unresolved external symbol __imp_sprintf hello_world…
Kaiyuan
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Send a bitstream in an FPGA board

I need to be able to send bitstream in a FPGA board. I use the Altera Cyclone III Development Board, I am looking for an option on Quartus for example to send bitstream, but I didn't find this either in the software nor on Internet.
Gilstaills
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Having FPGA to output sound on "line out" pin using verilog

I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1. I am new to hardware programming, therefore it just takes too much time for me to catch up with basics.…
ozgeneral
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Verilog error expecting a description

module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE); input [5:0] opcode,…
Caio Jose
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Correct arithmetic(cycle) shift in verilog

I'm new to verilog and am stuck on one curious moment. I'm trying to do a cycled leds blinking(green lights from left to right and red ones from right to left). I have 12 leds and am synchronizing my program with clock(CLK). I wanted to use…
greyxray
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