How to know if a std_logic has changed its value?

Question

I want to know every time a std_logic has changed from 0 to 1 and viceversa. So far I've made this, but the following error shows up: *Error (10819): Netlist error at prueba.vhd(15): can't infer register for b because it changes value on both rising and falling edges of the clock*

process(a)
        begin
            if (a'event and a='1') then
                --Do something
            elsif(a'event and a='0') then
                --Do something;
            end if;

        end process;

Your code looks OK and it'll work perfectly in simulation. However, not everything you write can be synthesised into hardware, including flipflops that respond to both clock edges... In this specific case, however, `b <= not a;` will do exactly what the above code does. — , Sep 09 '15 at 22:17

score 1 · Answer 1 · answered Sep 10 '15 at 00:20

See Altera discussion forum thread Error (10819). You're trying to use a dual data rate storage element to delay a signal by a half the clock period, besides how it would be useful not being apparent from your question DDR is only supported in I/O (google Altera dual data rate).

And as Brian notes you're simply making an inverted copy of a on b.

In detecting a transition on a where a is generated by clock clk you can generate a '1' on b every time there is a transition by:

process (clk)
begin
    if rising_edge(clk) then
        last_a <= a;
    end if;
end process;

b <= a xor last_a;

Where if the current value of a doesn't match the value of last_a the XOR product is '1', and where they match the product is '0'.

b could then be used as an enable for the next clock clk edge.

This is a variation on a synchronous edge detector using XOR instead of AND to detect both transitions.

Modeling this:

library ieee;
use ieee.std_logic_1164.all;

entity edge_detector is
end entity;

architecture foo of edge_detector is
    signal a, b, a_last:    std_logic;
    signal clk:             std_logic := '0'; 
begin

last_ff:
    process (clk)
    begin
        if rising_edge(clk) then
            a_last <= a;
        end if;
    end process;

    b <= a xor a_last;

CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if NOW > 200 ns then
            wait;
        end if;
    end process;

STIMULUS:
    process
    begin
        a <= '1';
        wait for 40 ns;
        a <= '0';
        wait for 50 ns;
        a <= '1';
        wait for 60 ns;
        a <= '0';
        wait;
    end process;
end architecture;

Shows:

(clickable)

Note the width of b is proportional to the clk -> a which is set by this simple simulation as half the clock period.

Also note that if a transitions on sucessive clk edges b will remain high, b really wants to be used as an enable.

How to know if a std_logic has changed its value?

1 Answers1