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Modelsim displaysCase statement choices cover only 4 out of 81 cases for my ethernet frame generation code I am getting this error after execution of my very long program in VHDL.It comprises of many case statements and case within case statements as well and of course many WHEN statements.However its said that When others => can be used only at the last statement of the code to avoid this particular error however there are many when statements used in the program.How to solve this issue?

susa1012
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  • Tough to tell you exactly what's wrong without any of your code – scary_jeff Aug 25 '15 at 09:20
  • Insert a `when others =>` just before each and every `end case;` . See if that works, and then go back to and make recover logic for each `others` so your code doesn't break. However if you have 81 cases i would think you could reduce and simplify your logic a bit. maybe divide all the sub cases into their own processes. Though hard to tell without seeing your code. – Ephreal Oct 13 '15 at 07:57

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When others => can be used at the last statement of each CASE statement, NOT just at the end of the code.

As Jeff says, without seeing your code there's not a whole lot more to say.

However, since you are covering 2 ** 2 cases out of 9 ** 2 I could make a wild guess you are covering all the '0' and '1' cases of a 2-bit std_logic_vector and ignoring all the metavalues. In which case you could replace

case my_slv is

with

case to_01(my_slv) is ...

and guarantee the metavalues are resolved to '0' or '1', but this sweeps all sorts of errors under the rug.

Far better to write an explicit test for any metavalues in the case statement. This will bring your simulations to a halt until you fix the real problem.

case my_slv is 
when "00" => ...
...
when "11" => ...
when others => report "Unreachable!" severity FAILURE;
end case;