Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

Stratix
Cyclone
Arria
MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

492 questions

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1 answer

How to connect my clockDivider into this verilog program with Quartus II

Code: TestBench.v: // ============================================================ // // Traffic light tester module. // // We clock the device as usual, supply reset, and eventually "push // the walk button" to activate the traffic light. // //…

verilog intel-fpga quartus

asked May 09 '15 at 22:53

avgvstvs

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4 answers

Need help for this syntax: "#define LEDs (char *) 0x0003010"

I'm doing programming of a softcore processor, Nios II from Altera, below is the code in one of the tutorial, I manage to get the code working by testing it on the hardware (DE2 board), however, I could not understand the code. #define Switches…

c casting c-preprocessor intel-fpga

asked Jun 10 '10 at 01:51

I'm a frog dragon

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1 answer

How to compile drivers on 3.0.32-yocto-standard

I am new to yocto and developing drivers. I got source code (alter_driver.c and Makefile) for the drivers but I don't have any idea how to compile and get altera_driver.ko file, so that I can load that drivers and use them. The version of yocto…

intel-fpga yocto

asked May 07 '15 at 05:02

TejaReddy

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1 answer

Simple Quartus compiling error related to device restrictions

I have a relatively simple circuit that I'm trying to compile. It requires 491 I/O pins, so I'm selecting a non-default device that has more than 456 (Cyclone IV GX with 508 user I/Os). The problem is that when compiling I receive this…

synthesis intel-fpga quartus

asked Apr 21 '15 at 17:25

Gaspa79

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2 answers

VHDL signal's Delay - Quartus

I faced a problem when using Quartus II from Altera. In the VHDL course, I have a problem about the behavior of VHDL variables VS signals. The theory says that the VHDL variables get its new value immediately. On the other hand , the signal's…

vhdl fpga intel-fpga quartus

asked Apr 09 '15 at 17:21

Heba

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1 answer

Is setting signal values to unitialized acceptable?

To achieve something in my VHDL code I'm currently doing: tmpOutput <= "UUUUUUUU"; Is that seen as something wrong entirely? Also, can this bring problems when synthesizing the design? Thanks a lot!

vhdl modelsim intel-fpga quartus

asked Mar 18 '15 at 20:57

Gaspa79

5,488
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63

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2 answers

Use dma transfert with Cyclone V Avalon-MM for PCIe

Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip-core named «Cyclone V Avalon-MM DMA for PCIe» to do dma transfert. But this ip-core does not support…

dma intel-fpga pci-e quartus qsys

asked Feb 11 '15 at 15:56

FabienM

3,421
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45

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1 answer

Edit top verilog component generated by Qsys

Is it possible to modify Verilog generated by Qsys before Quartus synthesis ? I designed a component under Qsys. I added the design.qsys file under my Quartus (14.0) project and selected it as «top-level». Qsys generate a verilog top component named…

verilog intel-fpga quartus qsys

asked Jan 29 '15 at 14:16

FabienM

3,421
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45

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1 answer

Code to add two 4-bit integers with verilog doesn't work. What is wrong?

I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem... module part2(SW, LEDG, LEDR); input [17:0] SW; output [17:0] LEDR; …

verilog xilinx hdl intel-fpga quartus

asked Jan 25 '15 at 01:12

OHHH

1,011
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34

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1 answer

Verilog: multidimensional registered outputs

I have some Verilog module with multidimensional outputs (to 7-segment LED panels of my DE1-SoC). I want to make the outputs registered. To test it, I give some dummy code to one of LED digits. Its RTL simulation passes OK, it's even compiled by…

verilog fpga system-verilog intel-fpga

asked Jan 06 '15 at 14:11

Felix

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3 answers

Is N-1 the largest term which could be used for Generic in VHDL

I am new to VHDL and I wanted to ask that what generic term could I use If i wanted to write any size of input vector which could be developed? GENERIC (n1 : integer); x:IN BIT_VECTOR(n1-1 downto 0); Is that a correct example?

math vhdl fpga intel-fpga

asked Dec 13 '14 at 04:02

JOHN

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1 answer

C to Fpga error with LCD under Altera DE2-70 board

I tried to display ASCII on the LCD, I am using a DE2-70 board and Handel-C using the Altera DE2 function library. This is the code I am compiling: set clock = external "N2"; #include "DE2.hch" void main(void) { DE2_LCD_LINE line; line =…

intel-fpga hardware-interface systemc

asked Nov 29 '14 at 21:45

user4259109

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2 answers

Is there a way to read WAV files off an SD card on a DE2-115 without using NIOS II?

I've been working on an SD card music player for a personal project and have been looking everywhere for an answer to this question. I simplified the Synthesizer example included with the board so that now all I need to do is get the audio data…

vhdl sd-card fpga intel-fpga nios

asked Oct 30 '14 at 04:34

mightynifty

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1 answer

Synthesizable wait statement in VHDL

I am writing a VHDL code to control AD7193 via SPI communication. ADC is controlled and configured via number of con-chip registers, DOUT/RDY (SPI_miso) goes low to indicate the completion of conversion. These are the code and timing characteristics…

vhdl spi intel-fpga

asked Sep 19 '14 at 01:20

lft

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1 answer

Why does my set_output_delay constraints cause warnings

I am trying to understand some warnings I get in Altera's TimeQuest. I started with the following constraints in my .sdc file set_output_delay -clock clk -max 3 [get_ports {data[*]}] set_output_delay -clock clk -min 1 [get_ports {data[*]}] It gave…

constraints fpga intel-fpga

asked Aug 22 '14 at 14:35

AxelOmega

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