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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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fork join algorithm on fpga

I want to transfer a fork-join problem in fpga. Fork-join in the sense that there will be many small components (> 100) accessing a memory component, processing input data (a few 32-bit vectors) for small amount of cycles (~50) without interactions…
user2609910
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Multiplexing more than 2 signals using Altera's LPM

How can I use busmux more than two input in Quartus? It seems I can use LPM_MUX instead, but I can't understand how to use it. Is there any easier way?
Alan42
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VHDL IF Statement in Case Statement

As you can imagine by seeing my code right there, I'm a beginner at VHDL so I'm really wondering why this isn't working as it seems it logically should work. In fact the part that isn't behaving the way that I'd like it to isn't doing anything at…
Guillaume Drolet
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Verilog VGA signal implementation: "stretched horizontal"

I'm implementing the XGA (1024x768) video protocol with an Altera FPGA. I have images displaying, with correct color and crisp vertical display (i.e., setting every nth vertical pixel to black results in a sharp horizontal line w/o aliasing).…
Connor Spangler
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How to instantiate megafunctions in Alteras Quartus-II FPGA IDE

I use the web (ie free) edition of Alteras FPGA IDE. According to the documentation, it hosts at least some of the Altera megafunctions. A response to an earlier tech forum enquiry indicates that it does. I’ve tried to use them, but without…
BruceV
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Altera FPGA vs Raspberry PI to detect LED with camera

I want to apply computer vision on an autonomous robot-car to position itself by detecting light sources (LED) on the field. I have an Altera FPGA and a Raspberry PI. Both will be attached with a camera. After researching on FPGA I understand that…
HieiFCB
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How to setup a dual adc in Altera Max10 FPGA?

Is there an example (VHDL) available how to setup the CSR interface for the Altera Max10 ADC converter? The Altera manual gives only limited information and only following description: It would be a big help to see the relevant interface in a…
Norick
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Programming FPGA with AVR Programmer instead of USB Blaster

I bought a MAX 10 FPGA 10M08 Dev Board and is has a JTAG on it that says to program with a Altera USB Blaster. Being impatient and all can I use my AVR Programmer and connect, assuming target power is used like so? AVR => JTAG =========== SCK ->…
Bob R
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VHDL VGA interface

I've been modelling a VGA interface on the DE0 board. I have the following model for a 640x480 display which refreshes at 60Hz: Main model: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY VGA is PORT (clk …
hoboBob
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floating point on altera: arithmetic or dsp cores?

i want to perform some floating point operations on altera fpga, but as far i understand there are two options from IP catalog: DSP core and arithmetic fp core what should i choose for some basic operations like add sub sqrt mult? Thanks
user2609910
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Warning about missing signal in VHDL process sensitivity list

I'm currently designing a simple multiple input SPI master in Quartus. Given it is a serial protocol, I have a serial clock and a signal that stores the current bit index. One of the processes I have written looks like this: store_bits :…
M Schubert
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VHDL Vending machine with an error in port map

I'm doing a vending machine project, the only problem I have is the port map for Seg where I get this error: Warning: COMP96_0411: reu.vhd : (363, 31): Actual of mode 'out' cannot be assigned to formal "x" of mode 'in'. Error: COMP96_0100: reu.vhd…
DNA5511
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verilog Linear feedback shift register random

module do2(rst,clk,cout); input rst,clk; output [7:0]cout; reg [2:0]D; reg [19:0]count; assign cout=out(D); always@(posedge clk) begin count = count+20'd1; if(rst) begin D<=3'b0; end else if(count==20'd100000)begin D[0] <=D[1]; D[1] <=D[2]; D[2]…
유정이
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How to use/declare an unsigned Integer value in VHDL?

I'm trying to design a basic Vending machine on a Altera DE1-SoC Board. My question comes from trying to code the State Machine that will control the vending process. How do you track the $ value being added jumping between states? I think the…
VKkaps
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hexadecimal seven segment display verilog

I've taken a project using verilog. We have two 4-bits number, a multiplexer(S0,S1) and four module(adder,substractor,and,xor). Output is 4 bit. I think it seems simple alu. I have written a verilog code that contains all of them as modules. I have…
user4134614
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