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I'm really new to FPGA and Verilog. I've been working on the Tri-SPI PHY controlling Noritake Itron VFD Display. One of the feature I want to implement is the framebuffer memory on the FPGA itself. I'm using the iCE40LP1K which has 64kbit BRAM (8Kbytes). But the Verilog BRAM Primitive is 4kbit and I required 3003 bytes for buffer.

The question is how can I cascade the BRAM ? in the datasheet (refer to iCE40 LP/HX Family Data Sheet, page 2-6) mentioned about using multiple BRAM. Is there a way that I can use multiple instance of SB_RAM40_4K? and the later treat as a one large mem array.

TinLethax
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2 Answers2

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Typically you would use some tools from the manufacturer of your FPGA. It's very common (probably even granted) that you have some wizard that will instantiate the IP you need.

In such wizard/editor/generator you will select the type of the memory you need (single/dual ported, width,depths,etc), and that tool will generate files that will instantiate required hw blocks. The wizard is responsible for doing that in the most optimal way, like stitching the blocks of ram using minimal width and maximal depth, in order to minimize the number of elements wasted on multiplexers.

Vlad
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  • Or you write Verilog that behaves like a RAM, and the synthesizer automatically determines depth, etc so you don't have to mess with vendor lock-in wizards. – Ben Voigt Nov 16 '21 at 15:43
  • @BenVoigt That's too, but isn't it too early for the beginner? He'll need to follow the rules he don't quite understand yet, the compiler might not be convinced enough to infer the required hw. – Vlad Nov 16 '21 at 20:01
  • I'm not convinced a beginner will do any better with a wizard that asks 20 questions about features of the BRAM that he has never heard of. – Ben Voigt Nov 16 '21 at 20:59
  • Totally forgot that I'm opensource guy and I stick to opensource tools (my toolchain setup: Yosys nextpnr). I want to stay away the IP module, it make my code less "open". Also I've seen people using logic cells as RAM but It'll runout quick (not event enough to make RAM from it). Anyway, I'll probably self-learning like last time I did with F1C100s ARM CPU that almost no one use it xD. – TinLethax Nov 17 '21 at 02:12
  • Well the inferred RAM stuff are not always working out as expected in my experience - it failed for me badly several times. The wizard, on the other hand, simply generates the file accordingly the technology. If one does not want to use that right away, one can still learn from it. In the end the final code will mostlikely look very similiar to the solution provided by the wizard. – Christian B. Nov 18 '21 at 19:22
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I be able to successfully use the BRAM as I wanted. It turns out that I just declare the register as 8bit array. And just make sure that there're input and output to/from that register array. Since I need 3004 bytes, this code below is how I make it work: (Note: names aren't important, Yosys is smart enough to map to SB_RAM40_4k. Also you change the array size and address bit width).

module BRAM(
input R_CLK,
input W_CLK,

input [7:0]BRAM_IN,
output reg [7:0]BRAM_OUT,

input [11:0] BRAM_ADDR_R,
input [11:0] BRAM_ADDR_W,

input B_CE_W,
input B_CE_R);

reg [7:0] mem [3003:0];

always@(posedge R_CLK) begin// reading from RAM sync with system clock 
if(!B_CE_R)
    BRAM_OUT <= mem[BRAM_ADDR_R];   
end 

always@(posedge W_CLK) begin// writing to RAM sync with Slave SPI clock.
if(!B_CE_W)
    mem[BRAM_ADDR_W] <= BRAM_IN;
end

endmodule
TinLethax
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