Synthesis getting stuck and not finishing due to this block of verilog code... any ideas why?

Question

This is the block of code causing the synthesis to get stuck

always @ (posedge M_AXIS_ACLK) begin
       if(force_enable && !stop_signal) begin
           for (j=0; j <31; j = j+2)begin
               buffer_data[j+buffer_counter]   <= (eqed_valid[j/2]) ? {23'b0 , eqed_vals[j]} : 64'b0 ;
               buffer_data[j+buffer_counter+1] <= (eqed_valid[j/2]) ? {23'b0 , eqed_vals[j+1]} : 64'b0 ;
           end
           buffer_counter <= buffer_counter + 32;
       end
    end

This is the block of code that sets up the force_enable and stop_signal which stops the buffer counter and the loop from running

/*
   SET THE BUFFER WIDTH FOR THE AXI STREAM. LETS HAVE 1024 BE DEFAULT VAL.
   Set the reset as well
*/
reg [31:0] buffer_max_counter;

always @ (posedge M_AXIS_ACLK) begin 
   if(!M_AXIS_ARESETN) begin
       buffer_max_counter <= 32'b0;
   end
   buffer_max_counter <= ( buffer_width > 16384 || buffer_width < 1024) ? buffer_width_default: buffer_width;
end


always @ (posedge M_AXIS_ACLK) begin
   if(!M_AXIS_ARESETN) begin
       counter_to_force_enable <= 0;
       stop_signal <= 0;
       force_enable <= 0; 
       for (i=0; i < 8192; i = i+1)begin
           buffer_data[i] <= 0 ;
       end
       valid_counter <= 0;
       eq_counter <= 0;
       buffer_counter <=0;
   end
   else begin
       if (M_AXIS_TLAST)begin
           stop_signal <= 0;
           buffer_counter <= 0;
       end
       if (enable_generator && !force_enable && !stop_signal) // staart the counter delay
           counter_to_force_enable <= counter_to_force_enable + 1;
       if (counter_to_force_enable >= 10 && (buffer_counter+32) < buffer_max_counter )begin //begin filling buffer
           force_enable <=1;
           stop_signal  <=0;
       end else if (counter_to_force_enable >= 10 && (buffer_counter+32) >= buffer_max_counter )  begin
            force_enable <= 0;
            stop_signal  <= 1;
            counter_to_force_enable <= 0 ; 
       end else begin 
            //do nothing
            force_enable <= force_enable;
       end
   end
end

I am guessing that the buffer_counter is the issue here since I am using it to index the array buffer_data and its not a constant.