Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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FPGA Timing Closure: How to constraint path between 2 clocks or how to force a hold on a path?

In a Lattice Verilog FPGA design, I have two PLL-generated clocks at the same frequency 125MHz (8ns) but the second clock is at 90° shift of the first clock: wire clk; wire clk90; //clk90 is clk with phase at 90° pllm pllm_inst(.CLKI(oscInternal),…

asked Feb 25 '22 at 23:21

gregoiregentil

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Rising Edge Led Counter Problems in VHDL

I'm new to fpga and VHDL in general (I'm using a fpga aprox. 2 weeks now). I am trying to create a project that lights up LEDs in order. First of all I made a falling edge detector for the button. And then I created a std_logic_vector for LEDs. But…

embedded vhdl fpga

asked Feb 23 '22 at 20:45

İbrahim Varola

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1 answer

How can I convert the serial signal from ADC to N-bit range signal?

My project goal is to design a 'heart rate module' using zed board and ppg sensor. I'm going to use Pmod as ADC for converting the analog signal from the ppg sensor to the digital signal so that the zedboard would be able to process it. there is a…

fpga spi

asked Feb 10 '22 at 02:51

bluemoon

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1 answer

Verilog ICE40 LED Driver as IO - SB_IO_OD, how to assign

New to verilog here. The Ice40 has an RGB led driver that can also be assigned as a normal IO. Trying to access the pin without setting it as IO will give this error one IceCube2 Error during constrained IO placement E2792:…

verilog fpga ice40

asked Feb 07 '22 at 00:28

Damien

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How to send a message from a Wi-fi board to cellphone

I am currently working on something that requires sending a message from FPGA board to a cellphone. I try to understand if it possible to connect to the FPGA board, a Wi-fi board that can deliver an sms. I have seen some suggestions in google, but…

wifi fpga

asked Feb 06 '22 at 13:19

Raul

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1 answer

What does the double slash(transition 0 --> 1) mean in SRAM datasheet?

The following image is from the datasheet of SRAM IS64WV51216BLL(page 15). It is a SRAM's write timing diagram.I don't know the meaning of double transitions for WE signal.I have circled it in red. SRAM write timing diagram Timing Diagram…

fpga digital-logic

asked Jan 29 '22 at 07:52

Jan

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How to store image in the FPGA for real time video processing?

I am implementing a video processing project in real time which comes from an HDMI input. The video input is going to have a green background, which will be replaced by an image stored in the FPGA in order to generate a new video with a different…

fpga xilinx vivado zynq vivado-hls

asked Jan 23 '22 at 09:46

Florence

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4 answers

Installing Vivado ML 2021.2 in CentOs but process is hang in 'Generating installed device list'

anybody can help me figure out why the installation is hanging on 'Generating installed device list' and how to solve it without starting the process all over. I am working on CentOs. Thanks in advance

centos fpga xilinx vivado

asked Jan 19 '22 at 08:19

Hellen P

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1 answer

Shifting in Verilog for multiplication

How does this line of code below works as the multiplication of (1024-31)? The code is intended to be synthesized for FPGA, so shifting is used instead of direct division. But what I do not understand is that how such shifting mimics the…

verilog system-verilog fpga digital digital-logic

asked Jan 11 '22 at 11:59

Blaco

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1 answer

Object is used but not declared in VHDL

I'm doing a BCD counter that can count up/down depending on the input signals. This is the requirement: This is my VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use…

vhdl fpga

asked Dec 31 '21 at 14:50

Garrick Jay

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1 answer

Programming xillinx cpld xc9536xl

Iam trying to program xillinx cpld xc9536xl and I'm using quartus prime lite edition latest version and I don't know which device to select while downloading quartus to help me applying code on xillinx cpld The devices are : Arria || device…

hardware fpga quartus

asked Dec 28 '21 at 09:49

Rafael Alfy

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1 answer

Program counter error while implement single cycle mips processor

I'm trying to implement single cycle mips processor using Verilog and I'm facing a problem while trying to test the code, it seems like the program counter isn't increasing after the first cycle but I can't figure out what is wrong. This is my…

verilog cpu-architecture fpga

asked Dec 25 '21 at 21:20

Abde

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1 answer

Xilinx PLanAhead crashing

I have installed xilinx ISE 10.1, 13.2 and 14.7.My code synthesizes but PlanAhead not opening on windows 10 64-bit.I googled and find a solution of replacing rdiArgs.bat file present in bin folder.I did that but still unable to launch Xilinx…

fpga xilinx vivado

asked Dec 23 '21 at 15:55

Zerox

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1 answer

VHDL: How can I execute the for loop once in process statement

I am new to vhdl and FPGA. For my project I need to use for loop. When I simulate my code it keeps counting and not stopping. I want my code to execute only once, my point is when the loop reaches it's limit code will stop executing. Here is my…

vhdl fpga

asked Dec 09 '21 at 12:26

radium88

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1 answer

Lattice ECP5 UART, no signal on terminal emulator

I followed this tutorial to the letter, but I'll to explain in detail what steps I took exactly. I have an ECP5-evaluation 85k board. I soldered bridges on R34/R35 (RX/TX) and R21 (connects LED D1 to RXD) I used my windows installation to run the…

fpga uart lattice

asked Dec 06 '21 at 16:48

Anteino

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