Is it possible to configure the same tdata width on the masters and slaves interfaces on the axi4-stream switch IP of xilinx?

Question

I have to connect an AXI-stream switch IP into my FPGA VIVADO design, the switch have two slaves and one master. The data width inbound is 32 bits and I need data width outbound to be as well, but no matter how I configure the IP, it seems that the data width outbound will be always equal to the half of the data width inbound (in case I would have 3 masters and 1 slave the bit ratio would be 1/3...). Anyone have any idea if it's possible to configure the IP as I need?

axi4-stream switch actual configuration

Answer 1

I have also been wondering about the AXIS signal widths of the AXI4-Stream Switch IP.

I think the confusion is caused by a faulty graphical representation of the AXIS interface connection in the block design. If you explode an AXIS interface on the Switch IP, the ports will all have the total width of all similar ports in every AXI interface e.g will the TVALID signal be [4:0] if the IP has five slave interfaces.

This image shows how 5*32 TDATA bits from five masters connects to one TDATA port in the synthesized design.