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Trying to find a way of implementing on an FPGA a multi channel delayed signal in real time. My intention is to A/D a continuous audio signal and split the signal into 10 output channels with each channel time delayed by differing delay amounts. The delays are to vary between 10us to 50us between each channel. I'm trying to attempt a beamforming of an audio signal.

user16145658
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Vox
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1 Answers1

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Could be done on a ram block large enough to hold the data for the longest required delay.

So there would be a ring buffer, samples would be written to a common head and read out at different offsets from the head, with offsets matching the desired delay. Even at few megasamples per second (unlikely for the audible sound?) you should be able to do that with a simple dual-port ram block (one writing port, one reading port), or even with a single port ram.

Vlad
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