Make a 4-bit adder fit in a single slice using Xilinx 7 series and CARRY4 in verilog

Question

I am trying to make a 4-bit adder using the CARRY4 primitive in the 7 series using verilog. The module I wrote was the following:

module fast_4adder(
    input  wire [3:0]   a,
    input  wire [3:0]   b,
    input  wire         c_in,
    input  wire         subtract,
    output wire [3:0]   sum,
    output wire         c_out);
    
    wire [3:0] b_sub;
    wire [3:0] carry;
    wire [3:0] prop;
    wire [3:0] gen;
    
    assign b_sub = b ^ {4{subtract}};
    assign gen = a & b_sub;
    assign prop = a ^ b_sub;
    assign c_out = carry[3];
        
    CARRY4 CARRY4_inst(
        .CO(carry),
        .O(sum),
        .CI(1'b0),  
        .CYINIT(c_in),
        .DI(gen),
        .S(prop));  
endmodule

I found the code for CARRY4 in the "7 series Libraries Guide".

Now I thought this would be implemented in a single slice and use 4 LUT's. But after implementation, it is using 20 LUT's.

Is there a way to make it use the single slice and use the 4 LUT's?

If i understand it correctly, even for the logic outside the carry4 you need at least 8 luts. (2 luts per bit). I do not think that you can do all of it in 4 luts. — Serge, Oct 16 '21 at 01:06
When I look at the data sheet of the 7 servies, a LUT is able to map 5 inputs on 2 outputs, so I thought it would be possible to have a[i], b[i] and subtract as an input and have generate[i] and propagate[i] as an output. Making it possible to use only a single LUT per bit. Or am I wrong? — Arne Cl, Oct 16 '21 at 07:42
You cannot ask the synthesizer to do all the job for you. Try to create those 5-input per-bit expressions yourself. — Serge, Oct 16 '21 at 12:14
I did that too and still had the same problem. The problem was that I had a MUX in front of the adder and the synthesizer put the mux in the adder module. — Arne Cl, Oct 17 '21 at 15:29

mcleod_ideafix · Answer 1 · 2021-10-16T18:35:55.137

Started a new project in Vivado, targetting an Artix 7-50 FPGA, with this sole module and defaults for synthesis and implementation, yields me this result (report_utilization):

1. Slice Logic
--------------

+-------------------------+------+-------+-----------+-------+
|        Site Type        | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs              |    4 |     0 |     32600 |  0.01 |
|   LUT as Logic          |    4 |     0 |     32600 |  0.01 |
|   LUT as Memory         |    0 |     0 |      9600 |  0.00 |
| Slice Registers         |    0 |     0 |     65200 |  0.00 |
|   Register as Flip Flop |    0 |     0 |     65200 |  0.00 |
|   Register as Latch     |    0 |     0 |     65200 |  0.00 |
| F7 Muxes                |    0 |     0 |     16300 |  0.00 |
| F8 Muxes                |    0 |     0 |      8150 |  0.00 |
+-------------------------+------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 0     |          Yes |           - |        Reset |
| 0     |          Yes |         Set |            - |
| 0     |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+------------------------------------------+------+-------+-----------+-------+
|                 Site Type                | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+
| Slice                                    |    1 |     0 |      8150 |  0.01 |
|   SLICEL                                 |    1 |     0 |           |       |
|   SLICEM                                 |    0 |     0 |           |       |
| LUT as Logic                             |    4 |     0 |     32600 |  0.01 |
|   using O5 output only                   |    0 |       |           |       |
|   using O6 output only                   |    0 |       |           |       |
|   using O5 and O6                        |    4 |       |           |       |
| LUT as Memory                            |    0 |     0 |      9600 |  0.00 |
|   LUT as Distributed RAM                 |    0 |     0 |           |       |
|   LUT as Shift Register                  |    0 |     0 |           |       |
| Slice Registers                          |    0 |     0 |     65200 |  0.00 |
|   Register driven from within the Slice  |    0 |       |           |       |
|   Register driven from outside the Slice |    0 |       |           |       |
| Unique Control Sets                      |    0 |       |      8150 |  0.00 |
+------------------------------------------+------+-------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.

By the way... shouldn't

assign b_sub = b ^ {4{subtract}};

be actually

assign b_sub = b ^ {4{subtract}} + subtract;

?

Because I had a multiplexer in front of my adder, vivado synthesized the mux in the module of the adder. So indeed the code works. and only uses 4 LUT. And for the latter part, you can better change the ".CYINIT(c_in)" into ".CYINIT(subtract)" but I wanted some more flexibility outside the module. — Arne Cl, Oct 17 '21 at 15:27

Make a 4-bit adder fit in a single slice using Xilinx 7 series and CARRY4 in verilog

1 Answers1