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I would like to know how I can do the following operations in this order:

First detect the falling edge of an input signal (rd), then wait for 15 ns and finally make the necessary changes in the variables, for example store the db_input 8bits vector into db_output 8bits vector.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ent1 is
    port
    (
        -- Input ports
        rd              : in std_logic;
        db_input        : in std_logic_vector (7 downto 0);

        -- Output ports
        db_output   : out std_logic_vector (7 downto 0) := (others => '0')
    );
end ent1;

architecture arch1 of ent1 is
begin

    process(rd)
    begin
        if (falling_edge(rd)) then
            -- Wait for 15 ns
            -- After the 15 ns save db_input into db_output
        end if;
    end process;
    
end arch1;
Alejandro Fernández Suárez
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  • are you trying to do this on an FPGA? without a clock that is somehow related to 15ns this will not be possible. – Tricky Nov 21 '21 at 19:55
  • unless you are literally trying to delay the signal by 15ns in your VHDL code only? – Tricky Nov 21 '21 at 19:56

1 Answers1

1

The following does what you asked for:

process
begin
  wait until falling_edge(rd);
  wait for 15 ns;
  db_output <= db_input;
end process;
Renaud Pacalet
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