Stack Overflow
Stack Overflow

Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions
0
votes
1 answer

Cypress S25FL256S Flash memory read delay issue

I am currently using an s25fl256s flash memory, but when I try accessing it (using an SPI master on an Artix7 FPGA) the first read access has a delay of 19 clock cycle (more or less) and afterward the data is received correctly, does anyone know…
Yan
  • 1
0
votes
1 answer

Trying to find Verilog Version of $realtime (SystemVerilog function)?

I'm trying to rewrite some Verilog files to be implemented on an FPGA. This means that I need to rewrite some SystemVerilog as Verilog so it can be synthesized. The code I'm using has realtime net types and calls the function $realtime and I have no…
Eliza
  • 1
0
votes
0 answers

Encountering Multiple Makefile Errors when Building RedPitaya Ecosystem and FPGA Image

I am doing research for college and part of my job is to use Xilinx Vivado to create and transfer fpga hardware programs to a RedPitaya STEMLabs 125-14. I am currently following the instructions provided by RedPitaya here (3.2.2.3 Build FPGA Image)…
sslerose
  • 1
  • 2
0
votes
1 answer

Button debouncing circuit full count based:

i am trying to practice debouncing on FPGA following the approach (full count based), that introduced in the book from Volnei ("Circuit Design with VHDL third edition"). A very important feature of this circuit is the way the timer is constructed,…
Ahmad Asmndr
  • 187
  • 1
  • 7
0
votes
0 answers

How to pass video with an efficent way to H.264 Encoder of Imx6 from Fpga memory

I'm working with a custom card that have customized Yocto distribution and use Imx6q SOC. This card purpose is mainly read video from Fpga and save it to a file. Fpga has trible buffer and generate an interrupt when Fpga memory was filled .Now I'm…
N.karagöz
  • 1
  • 2
0
votes
1 answer

How to change cases inside case structure LabVIEW FPGA

I've got simple code for generating different frequencies from Digital port of FPGA. But it does not change the frequency during the execution. If I stop the execution of the program and change the enum variable, the frequency will change. But…
Osiris74
  • 11
  • 2
0
votes
1 answer

Verilog If else "Signal not a constant" error

I am trying to instantiate modules inside various if else statements but i am getting the error with the first argument in the if parenthesis "signal is not a constant".All my arguments in the parenthesis of my if and if else statements are input…
Kyri Lynx
  • 5
  • 1
0
votes
1 answer

Inferring latch warning

I'm making this code, but I don't know how to deal with this warning. The warnings are on the process site. In this specifically process (boton) begin if (boton= '1') Then ienable <= '1'; else brojo <= '0'; bamarillo <=…
Massiel Angulo
  • 9
  • 4
0
votes
1 answer

Verilog Data Casting

I know it might seems a bit dumb for a question but i had to learn verilog by my own and sometimes i get a little confused about the basic things, so my question is ,when i read a file in verilog with signed decimals inside and special characters…
Kyri Lynx
  • 5
  • 1
0
votes
0 answers

Are two JESD204B FPGA masters able to form high speed serial link composed of multiple serial lines?

I need to realize point-to-point multigigabit connection between two FPGAs. For that I can use 4x6.25Gbps serial lines, and transport the data over optical link. The problem is, that the connection - realized over those 4 optical lanes - must look…
David Belohrad
  • 458
  • 5
  • 19
0
votes
0 answers

Using ftd2xx.dll in python, what is the approximate time to read and write registers?

Using ftd2xx.dll in python, what is the approximate time to read and write registers? My application is to access FT2232H via FPGA by SPI, which takes 300+ms to read a register. He's too slow. Do you have any ideas? note: bitmode is MCU Host Bus…
Fantexi
  • 1
0
votes
1 answer

NIOSII Softcore UART Interrupt

I try to get an UART IP core in combination with the NIOS2 (softcore) running on the Cyclone 10 LP evaluation board. So far everything works fine in polling mode. However, I cannot manage to get the interrupts running on the softcore. The FPGA is…
jodá
  • 342
  • 7
  • 25
0
votes
1 answer

How does JTAG flash memory programming work?

I am currently using Xilinx ZCU106 board, and I am curious about How does JTAG support flash memory programming. I can upload the boot images or hardware logic just by connecting JTAG USB cable to USB connector at the ZCU106 Board, and press the…
Jisung Kim
  • 133
  • 1
  • 9
0
votes
1 answer

VHDL - FPGA implementation - Pulse trigger generated only once on mutiple button pushes

Hello everyone I wrote some VHDL code that implement a UART-TX from my FPGA to my desktop. To trigger data sending I use the signal(debounced ofc) coming from the on-board switch. As long as the button is pressed data is being sent. Inevitably, for…
acefrrag
  • 41
  • 6
0
votes
1 answer

NIOSII with Remote System Update IP Core for Cyclone10LP does not execute

I am working on an update procedure for the Cyclone10LP FPGA with Quartus Prime 20.1.1. The platform design is done the following. The NIOSII Software Build tool for Eclipse Project is configured according to the .sopcinfo file. The NIOSII soft…
jodá
  • 342
  • 7
  • 25
1 2 3
…
99 100