Inferring latch warning

Question

I'm making this code, but I don't know how to deal with this warning. The warnings are on the process site. In this specifically

process (boton) begin
    if (boton= '1') Then 
    ienable <= '1';
    else
    brojo     <= '0';
    bamarillo <= '0';
    bverde    <= '1';
END IF;

END process;

--  University:   Universidad Tecnica Nacional(UTN)
--  Course:       Aplicaciones de FPGA
--  Developed by: Massiel Angulo Mejia
--  Module name:  Semaforo_Top
--  Date:         08/11/2022
--  File name:    Semaforo_Top.vhd
------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Semaforo is port (
   CLK_100MHz, boton     :in std_logic;   -- Define las entradas de 1 bit
   R, A, V       :out std_logic);         -- Define la salida de 1 bit

end Semaforo;

architecture Behavioral of Semaforo is
 signal rojo, amarillo, verde, puente, aca :std_logic := '0'; 
 signal brojo, bamarillo, bverde :std_logic := '0'; 
 signal q0, q1, q2, q3, q4, q5, enable, ienable  :std_logic := '0'; 
 signal r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 :std_logic := '0';
 signal a1, a2, a3, a4, a5, btn :std_logic := '0';
 signal v1, v2, v3, vr, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15 :std_logic := '0';
 
 
 component Contador5bits port (
    CLK_100MHz   :in STD_LOGIC;  -- Define la entrada de 1 bit
       reset      :in STD_LOGIC;  -- Define la entrada de 1 bit
       pausa      :in STD_LOGIC;  -- Define la entrada de 1 bit
       en         :in STD_LOGIC;  -- Define la entrada de 1 bit
       acarreo    :out STD_LOGIC;  -- Define la salida de 1 bit
       salida     :out STD_LOGIC_VECTOR(4 downto 0) :=(others => '0') -- Define la salida de 5 bits
 );
 end component;
 
    component FrequencyDivider
      generic(
         M :integer; -- Factor parametrizable en la instanciacion
         N :integer); -- Factor parametrizable en la instanciacion
      PORT(
         clk_in :in  STD_LOGIC;  -- Define las entradas de 1 bit
         clk_out :out STD_LOGIC); -- Define la salida de 1 bit
   end component; -- Termina la definicion del componente
   
begin

   process (boton) begin
    if (boton = '1') Then 
    ienable <= '1';
    else
    brojo     <= '0';
    bamarillo <= '0';
    bverde    <= '1';
END IF;

END process;


   --Inicio del decodificador para led verde
   v1    <=      not(q4)  and   not(q3)  and   not(q2)  and   not(q1)  and    q0;
   v2    <=      not(q4)  and   not(q3)  and   not(q2)  and   q1       and    not(q0);
   v3    <=      not(q4)  and   not(q3)  and   not(q2)  and   q1       and    q0;
   
   --Inicio del decodificador para led amarillo
   a1    <=    not(q4)  and   q3         and    not(q2)  and   q1       and   q0;
   a2    <=    not(q4)  and   q3         and    q2       and   not(q1)  and   not(q0);
   a3    <=    not(q4)  and   q3         and    q2       and   not(q1)  and   q0;
   a4    <=    not(q4)  and   q3         and    q2       and   q1       and   not(q0);
   a5    <=    not(q4)  and   q3         and    q2       and   q1       and   q0;
   --Inicio del decodificadotr para led rojo
   r1    <=    q4  and   not(q3)         and    not(q2)  and   not(q1)  and   not(q0);      
   r2    <=    q4  and   not(q3)         and    not(q2)  and   not(q1)  and   q0;      
   r3    <=    q4  and   not(q3)         and    not(q2)  and   q1       and   not(q0);      
   r4    <=    q4  and   not(q3)         and    not(q2)  and   q1       and   q0;      
   r5    <=    q4  and   not(q3)         and    q2       and   not(q1)  and   not(q0);      
   r6    <=    q4  and   not(q3)         and    q2       and   not(q1)  and   q0;      
   r7    <=    q4  and   not(q3)         and    q2       and   q1       and   not(q0);      
   r8    <=    q4  and   not(q3)         and    q2       and   q1       and   q0;      
   r9    <=    q4  and   q3      and    not(q2)  and   not(q1)  and   not(q0);      
   r10   <=    q4  and   q3      and    not(q2)  and   not(q1)  and   q0;   
   ---Reinicio en verde 
   vr    <=   q4   and  not(q3)  and    not(q2)  and    q1  and   q0; 
   
      --Inicio de instancia de las salidas
   rojo      <= r1 or r2 or r3 or r4 or r5 or r6 or r7 or r8 or r9 or r10;
   amarillo  <= a1 or a2 or a3 or a4 or a5;
   verde     <= v1 or v2 or v3;   
   
   enable <= ienable;
   --Instancia de las salidas
   R <= rojo and brojo;
   A <= amarillo and bamarillo;
   V <= verde or bverde;
   
    --Instancia del contador de 5 bits que cuenta 18s
   Cnt5bits :Contador5bits port map(
    CLK_100MHz   => puente,
    reset        => '0', 
    pausa        =>  '0',
    en           =>  enable,
    acarreo      =>  aca,  
    salida (0) => q0,
    salida (1) => q1,
    salida (2) => q2,
    salida (3) => q3,
    salida (4) => q4 
    );  
   
   
     -- Se realiza la instancia del componente
 divisor_1Hz :FrequencyDivider generic map(M => 100_000_000, N => 27) port map( -- Paso de parametros (M,N) en la instancia
      clk_in => CLK_100MHz,
      clk_out => puente
   ); -- Final de la instancia


end Behavioral;```

The thing in that part is that when you press boton enable is 1 and when boton is 0 brojo, bamarillo are 0 and bverde is 1.

Help me editing the process block to delete that warnings.

IEEE Std 1076.6-2004 RTL Synthesis (withdrawn) 6.2.1.1 Level-sensitive storage from process with sensitivity list "A level-sensitive storage element shall be modeled for a signal (or variable) when all the following apply: a) The signal (or variable) has an explicit assignment. b) The signal (or variable) does not have an execution path with as a condition. c) There are executions of the process that do not execute an explicit assignment (via an assignment statement) to the signal (or variable)." Identity assignments don't count. — user16145658, Nov 10 '22 at 22:29
Please replace the image of the warning message with the text itself. This makes it possible for other users to find this question when searching for the error message. — scary_jeff, Nov 11 '22 at 12:16
See [Warning (10631): VHDL Process Statement warning: inferring latch(es) for signal or variable](https://stackoverflow.com/questions/58148385/warning-10631-vhdl-process-statement-warning-inferring-latches-for-signal?rq=1) a possible duplicate (inferring latches isn't vendor specific). This shows up in the Related sidebar. — user16145658, Nov 11 '22 at 22:05

score 0 · Answer 1 · answered Nov 10 '22 at 18:43

When you synthesize a HDL code and you do not provide a sender to a signal at all time, you will always get a latch and a latch warning. In your case you do not provide a sender to brojo, bamarillo, bverde for the case when boton=1 and no sender to ienable for the case when boton=0. But in hardware there must exist a sender at any time, this is why a latch is inserted and provides the last assigned value to the undriven signal. In almost all cases latches inferred in this way are not wanted and bad design which will probably cause trouble later on in the design flow.

Inferring latch warning

1 Answers1