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I am currently using an s25fl256s flash memory, but when I try accessing it (using an SPI master on an Artix7 FPGA) the first read access has a delay of 19 clock cycle (more or less) and afterward the data is received correctly, does anyone know what causes the delay on the first read access ? according to the datasheet there should be no delays : https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17

I was expecting to start receiving the data on the first sclk rising edge that follws the LSB of my adress

Yan
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1 Answers1

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Be sure to observe the power up delay, tPU, describe on page 33 of the datasheet before trying to communicate with the device.

gkram
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