Questions tagged [fpga]

A Field-programmable Gate Array (FPGA) is a chip that is configured by the customer after manufacturing—hence "field-programmable".

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

There are four major manufacturers of FPGAs:

Xilinx, Inc.
Altera Corp. (now Intel FPGA)
Atmel Corp. (now Microchip Technology Inc.)
Lattice Semiconductor Corp.

When asking a question, specify a manufacturer and FPGA model family if applicable.

2742 questions

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1 answer

How do I include the base.dtbo/pl-final.dts for a reconfigurable FPGA in my Yocto Honister image (meta-xilinx xlnx-rel-v2022.1_update2)?

When porting to a new Yocto Honister distro and the meta-xilinx metalayer xlnx-rel-v2022.1_update2, the base.dtbo device tree overlay is not generated anymore for dynamic FPGA reprogramming. How do I get the generation running again?

asked Sep 29 '22 at 08:33

Xerusial

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1 answer

"Serial Loader Device is missing" during Convert Programming File with Quartus Prime

I try to convert multiple SRAM object (.sof) files to one JTAG indirect configuration file (.jic) using Quartus Prime, however I always receive the following error message. Serial Flash Loader device is missing I use the Cyclone 10 LP Evaluation…

intel fpga quartus intel-fpga

asked Sep 28 '22 at 12:56

jodá

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0 answers

Error calling the kernel: error code is: -6 on openCL kernel

my question is little different than that being asked on this platform, but I think it is related to programming. I am using vitis and alveo accelerators. They basically have a host program( written in C++) and than a openCL file, which is also kind…

c++ opencl fpga

asked Sep 27 '22 at 19:15

Manu Chaudhary

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1 answer

Write and read to a register created in FPGA by verilog at the same time

What will happen if I read and write a register both at the posedge of the clock cycle? I encountered this question while learning a RISC-V pipeline implementation which uses the technique called double bump to avoid this question. I wonder why this…

fpga

asked Sep 21 '22 at 05:59

haomingyu_ZJU

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1 answer

Start up behavior of moving average filter is different between pre and post synthesis functional simulation

I've implemented a moving average filter (in Verilog), based on an article I read which performs differently pre and post synthesis. The design implements $y[n]=y[n-1]+x[n]-x[N-1]$. module ma_width #(parameter WIDTH =16)( new_sample, en, …

verilog simulation system-verilog fpga synthesis

asked Sep 20 '22 at 16:05

jrive

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Is my Verilog code synthesizable/correct?

I am trying to write a module to "blur" a raster image - take the average of a 3x3 pixel sliding window across the image. The input image is a series of bytes with RGB values of the pixels, row by row, from bottom to top (similar to bitmap). It…

verilog fpga

asked Sep 15 '22 at 13:29

chris

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0 answers

how to create a Tcl file in Vitis

I am trying to learn how to create the TCL file from Vitis so I can use it to re-create the same project later. I have done the same in Vivado, but Vitis seems different. how can I re-create a project by using TCL or any other file in…

tcl fpga vivado vitis-ai

asked Sep 15 '22 at 08:17

Sameh

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0 answers

In xilinx vivado how to find the maximum frequency in the report similar to xilinx 14.7

Timing Summary: Speed Grade: -1 Minimum period: 4.979ns (Maximum Frequency: 200.844MHz) Minimum input arrival time before clock: 1.459ns Maximum output required time after clock: 0.833ns Maximum combinational path delay: No path found This is…

fpga

asked Sep 15 '22 at 07:16

sumanth

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2 answers

Hexadecimal Addressing

I'm confused about the bottom statement from this API's documentation. The API is meant to control an FPGA using Python commands. From the first line I can conclude that the 0x07 is the address of the input wire, but how does bit 3 get written with…

api hex fpga memory-address

asked Aug 31 '22 at 03:16

PrematureCorn

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1 answer

Xilinx Alveo U50 ES3 FPGA, FPGA_RXD_MSP pin meaning?

I found on https://github.com/Xilinx/XilinxBoardStore/blob/2020.1.1/boards/Xilinx/au50/production/1.0/part0_pins.xml two pin names I dont understand. What are purpose of

fpga xilinx

asked Aug 23 '22 at 17:15

A.Mem

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0 answers

Eigen::MatrixXf FPGA search

I have millions of Eigen fp32 , Eigen::MatrixXf::Random(1, 512) matrix subtract and also squaredNorm are using for calculations. Is FPGA can make it faster than the CPU and what magnitude ? Is there any FPGA in the market that I can evaluate = …

fpga eigen3

asked Aug 15 '22 at 19:18

AILORD

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1 answer

wire output can be used as an inside variable?

i am learning verilog and i am doing practice questions on https://hdlbits.01xz.net/wiki. one of the questions is: so my answer was: module top_module( input a, input b, input c, input d, output out, output out_n ); …

verilog system-verilog fpga hdl

asked Aug 07 '22 at 22:01

WoWPro71

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1 answer

Adding large numbers in FPGA in one clock cycle

If I have a VHDL adder which adds two numbers together: entity adder is port( clk : in std_logic; sync_rst : in std_logic; signal_A_in : in signed(31 downto 0); signal_B_in : in signed(31 downto 0); …

vhdl fpga timing

asked Aug 05 '22 at 12:13

arb01234

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2 answers

Will 'typedef logic' generate a register when using it instead of a 'wire', in SystemVerilog?

Having the following SystemVerilog code: module my_module( input wire [31:0] my_net ); ... endmodule ... ... wire [31:0] my_net; assign my_net = ...; my_module m(my_net); What are the consequences (at synthesis time) of change the my_net…

verilog fpga register-transfer-level type-definition

asked Aug 02 '22 at 14:34

Dan

2,452
20
45

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1 answer

1KHz Binary Counter: output stuck at 0000

I'm trying to build a 1KHz binary counter in Verilog for use in an FPGA. I want to get it to work in a single .v file before separating each module into it's own file and getting practice in calling modules that way. As far as I can see, I've set up…

verilog fpga

asked Aug 01 '22 at 22:39

CE_guy

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