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I'm having trouble understanding how to calculate Setup slack and Hold slack correctly. According to the Intel Quartus Timing Analysis manual, Setup slack is calculated as Data Required Time (Setup) minus Data Arrival Time, and Hold slack is calculated as Data Arrival Time minus Data Required Time (Hold).

However, no matter how I calculate it, my results never seem to match up. I've been spending a lot of time trying to figure out the concept of hold and setup, but it's been challenging. Is it normal to find these concepts difficult to grasp? Can someone explain the correct algorithm for calculating Setup slack and Hold slack?

I would greatly appreciate any help or insights.

Data Path Timing Analysis 1

Data Path Timing Analysis 2

I've referred to the following articles as my reference: user guides

Mikef
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King Fire
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1 Answers1

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Setup and hold slack are part of the timing analysis done by FPGA and digital design tools. Timing analysis is a check to ensure that data is passed reliably from component to component in clock-logic circuits.

The free book by H. Deblumont found at the following thread on the Xilinx/AMD has lots of introductory discussion about timing analysis and setup/hold slack.

FPGAs With VHDL : First Steps

Mikef
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gkram
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