(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.ALL;
use ieee.math_real.all;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

port 
(
    
    signal Led_7                :   out std_logic := '1';
    signal Led_6                :   out std_logic := '1';
    signal Led_5                :   out std_logic := '0';
    signal Led_4                :   out std_logic := '0';
    signal Led_3                :   out std_logic := '0';
    signal Led_2                :   out std_logic := '0';
    signal Led_1                :   out std_logic := '0';
    signal Led_0                :   out std_logic := '0';
    signal Binary8bitLED                :   out std_logic_vector(7 downto 0) := "00000000"

);

architecture rtl of i2s_interface_1 is

signal Binary8bitData               :   std_logic_vector(7 downto 0) := "10010110";
signal Binary8bitdivider            :   std_logic_vector(7 downto 0) := "00001010";

begin
        prescaler: process(clk)     
    begin

    Binary8bitLED   <= std_logic_vector((to_signed(to_integer(to_signed(Binary8bitData)) /                    (to_integer(to_signed(Binary8bitdivider))))),8);



    Led_7 <= '1';
    Led_6 <= '1';
    Led_5 <= '1';
    Led_4 <= '1';
    Led_3 <= '1';
    Led_2 <= '1';
    Led_1 <= '1';
    Led_0 <= '1';
    
    -- Binary8bitLED Output here

    end process;
end architecture;

The code is a snippet of the relevant bits. I want to divide (Binary8bitData / Binary8bitdivider) to get a remainder of 15 so "00001111" - > Binary8bitLED

convert the remainder into the LED's on my FPGA.

its a test code to divide binary numbers and I'm looking to show the answer through 8 LED's.

10010110 / 1010 = 15 r 0.

Adding the missing part of the entity declaration, commenting out the use clauses for Synopsys packages (leaving IEEE std_logic_1164 and numeric_std), commenting out the process sensitivity list and adding an explicit wait statement and `Binary8bitLED <= std_logic_vector (signed(Binary8bitData) / signed(Binary8bitdivider));` analyzes (compiles). Package numeric_std contains signed and unsigned division "/" operator overloads unlike the Synopsys packages here with a quotient length of 8. Provide a [mcve], package math_real is not used as shown either. — user16145658, Jul 11 '23 at 20:59
The output should look like [this](https://i.stack.imgur.com/HPpx0.jpg). The use of signed division is performed based on the original assignment statement. The waveform here shows both signed decimal and hex values. A [mcve] here implies removing the process sensitivity to clk which isn't declared a `wait for 10 ns; wait;` was appended to the process. Some simulators allow the use of top level signals with default values. — user16145658, Jul 11 '23 at 21:12
Hello user16145658, In your simulated example. result of the division writes to the left 4 bits and the right most 4 bits becomes inherited by the Binary8BitDate. `Binary8bitLED <= std_logic_vector (signed(Binary8bitData) / signed(Binary8bitdivider));` 10010110 ----------- = 11110110 00001010 This division is incorrect. it should come out as 00001111. Could this mean the above line you sent (thank you) needs the <= changed to => to correct this with a (others "0") appended to it. `Binary8bitLED => std_logic_vector (signed(Binary8bitData) / signed(Binary8bitdivider)) and (others "0"); — Keith Beech Hall, Jul 12 '23 at 13:28
Hello user16145658, With the amended line, i have an error to not use "/" operator. — Keith Beech Hall, Jul 12 '23 at 13:40
Hello user16145658, I will try and create another work space with just this problem and post the full code here in text later. — Keith Beech Hall, Jul 12 '23 at 13:43

score 2 · Answer 1 · answered Jul 11 '23 at 11:47

2

to_signed(Binary8bitData) cannot find an appropriate function, as slv to signed conversion can be done by a simple type conversion rather than a conversion function:

signed(Binary8bitData)

But you have a further issue: You have included the non-standard synopsys std_logic_arith package. This has duplicate definitions of signed and unsigned types defined in the VHDL standard numeric_std package. This means the compiler does not know which version of to_signed or signed type you want, and hence all will be invisible. You should delete the line:

use ieee.std_logic_arith.ALL;

from your code.

answered Jul 11 '23 at 11:47

Tricky

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With the changes above i get the same error. (VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument. `library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; Use IEEE.STD_LOGIC_UNSIGNED.ALL;` `Binary8bitLED <= std_logic_vector((signed(to_integer(signed(Binary8bitData)) / (to_integer(signed(Binary8bitdivider))))),8);` That's the new line added. Still doesn't like converting it. – Keith Beech Hall Jul 11 '23 at 12:32
`Integer` => `signed` conversion required two paramters - the value to convert and the length of the resulting vector. Your original `to_signed` call does not have the 2nd operand, and your modified code removed the `to_signed` function for the integer -> signed conversion. – Tricky Jul 11 '23 at 14:39
Thanks Tricky for your support. `Binary8bitLED <= std_logic_vector((to_signed(to_integer(to_signed(Binary8bitData)) mod (to_integer(to_signed(Binary8bitdivider))))));` Adding to_ back does remove the first error, now it complains about the integer. `(VHDL-1272) type error near 'binary8bitdata' ; expected type 'integer'` i expected both signals to sign and then convert to integer for the division process, then back to signed and converted into std_logic_vector. is it best to separate this line out into smaller parts? or should i be asking how you would implement this? – Keith Beech Hall Jul 11 '23 at 16:56
I don't think you understood my post. You need both `to_signed` conversion function and `signed` type conversion in your expression. `to_signed` requires a 2nd parameter specifying the resulting length also. – Tricky Jul 12 '23 at 05:51
I would also not use the / or mod operators if this is for an FPGA implementation. It can produce large slow logic and some tools (vivado for example) won't compile it unless the divisor is a constant power of 2. – Tricky Jul 12 '23 at 05:54
Hello Tricky, I am using an FPGA, if im not going to use / or mod, is there another way to do this? Thank you. – Keith Beech Hall Jul 12 '23 at 13:42

(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument

1 Answers1