How to synthesize UDP (User defined primitive) for fpga

Asked Jun 23 '23 at 04:20

Active Jun 23 '23 at 18:42

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I am a newbie with fpga design. I am trying to synthesize a udp file for fpga prototyping. Currently, Vivado and synplify cannot support synthesis for UDP file. Anybody have the solution, please help me ! I intend to create a model for UDP with verilog. Is this solution okay or not ? Thanks in advance !

Trong

edited Jun 23 '23 at 18:42

ndc85430

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asked Jun 23 '23 at 04:20

Trong Tran

see [SO udp](https://stackoverflow.com/questions/73244933/synth-8-27-primitives-not-supported-in-vivado) – Mikef Jun 23 '23 at 11:41
Hi @Mikef, Thank you for your link. This is what I need. – Trong Tran Jun 25 '23 at 14:08

How to synthesize UDP (User defined primitive) for fpga

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