Questions tagged [asic]

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a specific application, rather than being a general-purpose IC.

See Wikipedia page on ASICs.

97 questions

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votes

2 answers

IC design/verification with Python

I see a lot of jobs in this field asking for Perl and Python scripting experience. Very little C programming if any. Where HDL is the main focus (verilog,, VHDL) along with digital system design knowledge. Is Python generally used in these job…

asked Sep 10 '15 at 11:43

cc6g11

-1

votes

1 answer

Area optimization for a custom library using Synopsys Design Vision

I write a custom library for synopsys design vision which only consists of XOR, NOR, and IV (inverter or NOT). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of NOR gates. I write the library as…

synthesis circuit synthesizer asic

asked Jun 14 '14 at 21:07

ebi

-1

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1 answer

Overwriting a register in two different always blocks

I am trying to write a verilog code for an image labeling algorithm...The algorithm has several stages in which each is to be written as a separate always block...however, as far as I know, a variable (of type reg) used in one always can NOT be used…

verilog fpga system-verilog asic

asked May 04 '14 at 07:36

user84310

-2

votes

2 answers

I am trying a counter that gives me upcounts in the following manner?

I am trying to make a counter that depends on a signal. The signal is high for two cycles and low for next two and this continues till the end. During the high pulse, count should start from 0, 1 . When the pulse is low count is 'x and from next…

verilog system-verilog register-transfer-level asic

asked Sep 02 '18 at 12:49

s.21

-2

votes

1 answer

Verilog [cross module resolution error] when expanding the definitions

I've been getting a cross-module resolution error, when the compiler expands the definition as follow: in file, say path_defines.vh (where the definitions is at): `define apple aaaa.bbbb.cccc.\pie[0] .dddd.eeee I'm using the "\" character…

compiler-errors verilog system-verilog hdl asic

asked Jul 03 '17 at 01:44

TheSprintingEngineer

-2

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3 answers

What will happen in synthesis if a signal is only defined inside reset logic in always_ff?

Let's say I've following code: always_ff @(posedge clk, negedge rst) begin if (~rst) begin bad_singal <= '0; good_signal <= '0; end else begin // do something // bad_signal is not used here or anywhere in design. …

verilog system-verilog asic

asked Mar 08 '17 at 21:44

newbie

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-5

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1 answer

How do Hardware Description Languages differ from General Purpose languages at the low level?

Question: How do Hardware languages (HDLs) differ from general purpose languages such as Python, Java, etc. In particular, what is the primary trade-off that causes general purpose languages to be sub-optimal for FPGA's when compared to VHDL and…

vhdl verilog fpga hdl asic

asked Aug 22 '16 at 22:07

Tucker

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