Highest Voted 'asic' Questions

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ASIC design - combinational logic

I had an interview a few days back and this was the question they asked me in one of the rounds: A mux which gives output a when select line is 1 and b when it is 0. The output is represented as C. This has to be implemented with and and not gates…

asic

asked Nov 24 '11 at 00:00

Ram

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Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simvision tool?

I am trying to display coverage (in terms of percentage) for a specific bin within a coverpoint. I am able to display the coverage percentage of a coverpoint but not the coverage percentage for individual bins within the coverpoint. covergroup cov_a…

system-verilog hdl asic

asked Jan 04 '23 at 02:08

user20923807

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-> operator in the middle of a property

I understand that [-> m] is a non-consecutive GoTo operator and can be used as (e.g.) @(posedge clk) a |=> b [->2] ##1 c; But I came across an example, where I see (in the middle of a property), a -> b. What does that mean? Does it mean if a is…

system-verilog asic

asked Jul 24 '22 at 16:04

CCRCCR

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Why this process is executed when the simulation starts

This is a simple entity just to know the usage of "process" My question is: Why the process is executed when the simulation just starts? I think the process wakes up when the signals in the sensitivity list change, but in this example, the…

vhdl fpga hdl modelsim asic

asked Jan 06 '22 at 10:56

Hao Alessandro

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What does Trace Enable mean in Lauterbach?

I am working on Lauterbach to collect the traces from a sink where a processor is a source. This is done using a 'step' operation and while doing so, in the midway on the trace.list window I am displayed with 'TRACE ENABLE' in red (as attached in…

emulation trace lauterbach asic

asked Oct 19 '21 at 13:54

QTip

70
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Systemverilog function synthesis - automatic vs static

In the context of combinatorial logic synthesis (not simulation): When should a function be declared as automatic ? When should a function be declared as static ?

system-verilog vlsi asic

asked Feb 20 '21 at 00:59

shaiko

159
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Using firmware on ASIC simulation environment

We are designing an ASIC that is based on an ARM CPU and multiple other hardware engines. These engines are controlled through memory mapped registers accessible by the CPU AHB port. Currently, we have simple tests written in C that are compiled,…

verification firmware asic

asked Dec 03 '20 at 21:52

Marcus

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1 answer

Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process

I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and everything in between. My project consists of a…

asic

asked Jun 10 '11 at 05:41

Anon21

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Does enum literal deceleration of states guarantee a glitch free state machine?

does the enum literal deceleration of states for a state machine, guarantee a glitch free behavior as same as one would to assign order as below to the states? enum { a,b,c} states; //vs if you were to declare parameter a = 3'b000; parameter b=…

verilog system-verilog state-machine asic

asked Jan 28 '19 at 16:24

Mel

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1 answer

How to replace combinational memory with ASIC cell in Chisel

I am trying to do ASIC synthesis for Rocket processor which is written by Chisel. It automatically generates *.conf and *.behave_srams.v files. So, I can easily replace SeqMem with ASIC SRAM. However, for "Mem" which is combinational memory is…

synthesis chisel asic rocket

asked Dec 18 '18 at 22:45

sungbo

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Combinational circuit : Output 2s complement only when select line is high

I want to design a gate-level combinational circuit that implements the below logic. Is it possible to do it without using Adder? ... input wire [3:0] in, input wire sel, output wire [3:0] out ... assign out = ({4{sel}} & (~in + 1)) |…

verilog register-transfer-level asic

asked Nov 12 '17 at 04:18

ashishdevre

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Implementing a VHDL binary search on a std_logic_vector [vhdl]

I'm attempting to create synthesizable VHDL (function or procedure) for an ASIC (it must be part of the ASIC) that will look for the first '1' in a standard_logic_vector and output which vector position that '1' was in. For example, I have an 8-bit…

vhdl binary-search asic

asked Oct 20 '17 at 16:25

jtw71

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Prepone Region in SystemVerilog

In SystemVerilog simulation, the prepone region is one of the several regions in a given time slot. What is the actual purpose of this region? Can anyone explain this with a valid example?

system-verilog vlsi asic

asked Sep 21 '17 at 02:50

Aravind

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Modelsim error "is not an operator symbol"

I wrote code, but ModelSim said : "unsigned2hexstring" is not an operator symbol. What should I change and how use mine package like library? Is it will like : library ieee; use ieee.std_logic_1164.all; use work.prosoft_std.all ??? library…

vhdl fpga modelsim asic

asked Nov 15 '16 at 11:30

Nikita Malyshev

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1 answer

SVA Property for a simple waveform

Waveform:- I did a property as: property p1; a |=> (b == 1)[=2] ##1 (c == 1)[=2] endproperty But this property doesn't work well for this waveform, it isn't working for 3 or more "b's" before the "c's" and it isn't working for "c's" after the…

verilog system-verilog verification asic system-verilog-assertions

asked Jun 26 '16 at 01:03

Charlie Walken

11
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Questions tagged [asic]