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I write a custom library for synopsys design vision which only consists of XOR, NOR, and IV (inverter or NOT). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of NOR gates. I write the library as flows:

library(and_or_xor) {
cell(NOR) {
  area : 1000;
  pin(A) {
    direction : input;
  }
  pin(B) {
    direction : input;
  }
  pin(Z) {
    direction : output;
    function : "(A+B)'";
  }
}

cell(IV) {
  area : 1;
  pin(A) {
    direction : input;
  }
  pin(Z) {
    direction : output;
    function : "A'";
  }
}

cell(XOR) {
  area : 1;
  pin(A) {
    direction : input;
  }
  pin(B) {
    direction : input;
  }
  pin(Z) {
    direction : output;
    function : "A^B";
  }
}
}

Here, I have removed timing and input capacitor for the sake of saving space. I set area of NOR to 1000 and XOR and IV to 1 so I can use area optimization to replace unnecessary NORs with XOR and IV. I compile my combinational logic using set_max_area 0 and then compile_ultra -exact_map -no_design_rule -area_high_effort_script.

Problem is no matter I set NOR area to 1 or 1000, I will get the same result (# of NOR). It seems the area optimization trick doesn't work. Do you know why? How can I minimized NOR?

Thanks

ebi
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1 Answers1

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I don't think it's possible to create a NOR gate from XORs, so it doesn't matter how cheap they are; XOR is not functionally complete.

You can check that the synthesis is properly inferring XORs by giving it a problem which should not contain any other gates, such as a unary XOR:

wire [15:0] foo;
wire bar;

assign bar = ^foo;
Guy
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  • But it is possible to reduce a number of NOR gates to XORs in some cases. I know it is not possible to remove NOR from circuit but I want to minimize them. So, you are saying it is already minimized? – ebi Jun 16 '14 at 22:36
  • Effectively yes. It's possible for the tool to find local minima that it can't back itself out of but most likely there's nothing left that maps well into an XOR. – Guy Jun 16 '14 at 23:30