What will happen in synthesis if a signal is only defined inside reset logic in always_ff?

Question

Let's say I've following code:

always_ff @(posedge clk, negedge rst) begin
   if (~rst) begin
      bad_singal <= '0;
      good_signal <= '0;
   end else begin
      // do something
      // bad_signal is not used here or anywhere in design. 
      if (some condition)
         good_signal <= 1'b1;
   end
end

What will happen to bad_signal in synthesis? Will the synthesis tool optimize away the flop as it's not used anywhere in the design?

score 4 · Answer 1 · answered Mar 08 '17 at 22:18

4

If a signal or register doesn't drive anything, then yes -- any competent synthesis tool will trim it away, regardless of how it is set. Many synthesis tools will report a warning when this occurs.

answered Mar 08 '17 at 22:18

score 1 · Answer 2 · answered Mar 10 '17 at 01:31

1

It should infer a latch technically.

answered Mar 10 '17 at 01:31

Shankhadeep Mukerji

628
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35

But this is safe to waive. Isn't it? – newbie Mar 13 '17 at 00:36
@newbie yes indeed it is. Better not to use for such a scenario. – Shankhadeep Mukerji Mar 14 '17 at 00:16

score 0 · Answer 3 · answered Mar 09 '17 at 06:14

0

If it not used it will be optimized away. If it is used somewhere it will be tied to the ground since its value is always 0.

answered Mar 09 '17 at 06:14

Alper Kucukkomurler

1,706
2
13
19

What will happen in synthesis if a signal is only defined inside reset logic in always_ff?

3 Answers3