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Questions tagged [asic]

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a specific application, rather than being a general-purpose IC.

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a specific application, rather than being a general-purpose IC.

See Wikipedia page on ASICs.

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Asynchronous FIFO depth calculation

I was required to calculate how long it will take to fill an asynchronous FIFO. For example: Assume that module 'A' wants to send some data to the module 'B'. The frequency of module A is 80MHz. The frequency of module B is 50MHz. The burst length…
Kun liu
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Real world DRAM write only application

I am eager to know if there is any real world application which includes following scenario: Megabytes of continuous write-only to DRAM simultaneously from all (three or more) A53 cores (or any other Arm cores) – throughout the application as the…
Nee
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SystemVerilog: writing into an array using a write pointer

imagine that I have a certain buffer of bytes and a write pointer for this buffer, like: reg[N-1:0][7:0]mybuffer; reg[$clog2(N+1)-1:0] wptr; where wptr points to the next position in the buffer where I want to store incoming data. Now, imagine that…
arandomuser
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How can I use genvar variable to access input signals?

I have a module with 30-vector inputs.. I need help in the for loop assignment. module test ( input [3:0] i0, input [3:0] i1, input [3:0] i2, ... input [3:0] i29 ); wire [3:0] int_i [0:29]; genvar j; generate for (j=0; j<30; j=j+1)…
Tushar Garg
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How to assign initial value to an input reg: Design compiler delete the assignment

I'm newbie in ASIC design. I have a design with for example two inputs a ,b. I'm using the following code for initialize these two signals. But the Design compiler generating a warning that the register "a" is a constant and will be removed. When…
user214497
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Why is the following clock multiplication Verilog code not working for me?

I am trying to generate a clock which is (3/16) of the system clock. So, I have decided to generate a 3x clock from the system clk and then (1/16)x clock from that. Right now, I am stuck at generating just the 3x clock. I am doing this by…
Timothy Grant
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Read Variable length string in a file using SystemVerilog

Suppose I have variable length string as below: Write
Read
Write
Write
How do I read in SystemVerilog or Verilog using file operations. I know…
Vishwasu Deshpande
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I am facing the "Size mismatch error" in verilog

parameter N1 = 5; parameter N2 = 5; wire [(N1+N2-1):0] seckey [8:1]; shiftreg #(.depth(N1+N2-1)) sr1( .clk(clk), .reset(reset), .data_in(muxout[1]),…
Harshit Kumar
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increasing the PPA limitation of a design

i finished creating a design in vhdl, of the algorithm sha256. now im trying to get my design level higher by understanding how to change the code so i will get higher result of power, performance and area. the end game goal is trying to get the…
shmulikm
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ACP and DMA, how they work?

I'm using ARM a53 platform, it has ACP component, and I'm trying to use DMA to transfer data through ACP. By ARM trm document, if I understand it correctly, the DMA transmission data size limits to 64 bytes for each DMA transfer when using ACP. If…
Leslie Li
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Propagational delay in circuits

which is better for accurate proportional delay: spice simulation method or calculation using elmores delay (RC delay modeling)
Qurat
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VHDL: How to rapidly skip over registers that I don't care about?

I have N registers that are M bits wide. All the registers are filled with values but I only want to sample those registers that fits a certain pattern, such as only look at the registers whose MSB is a 1. On every rising edge of a clock I want to…
jtw71
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same source, different clk frequency(multi-clock design)

how to handle the multi-clock design signals with the clock generated from the same source? For example, one clock domain is 25Mhz the other one is 100Mhz how can I handle the data bus from 25Mhz to 100Mhz and also 100Mhz to 25Hhz? don't want to…
user2442045
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Error: /..integrator.vhd(47): near "process": (vcom-1576) expecting IF VHDL

I'm trying to add two registers storing signed bits one of 3-bit[FRQ(2 downto 0)] and other is 7-bit[PHS(6 downto 0)]...and has to store the addition of these two registers in 7-bit register [PHS(6 downto 0)]. Thanks in advance for your helpful…
Gaurav Singh
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Complexity slowdown for stored program computer

The Wikipedia page on Turing machines states that a universal Turing machine is slower than the machines it simulates by at most a log factor. I was curious - what is the equivalent in real life, comparing a pure hardware solution (non stored…
Andrew
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