Highest Voted 'asic' Questions

3

votes

2 answers

Why delays cannot be synthesized in verilog?

I have always read that delays declared in a RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code. For example: x = #10 y; will be considered as x…

asked Jul 12 '14 at 07:29

Anand

363
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11

3

votes

2 answers

Case statement in verilog

I came across priority encoder design and found out a new way to do it using a case statement. The only thing that is confusing is, does a case statement give priority to cases? Example: case(1'b1) A[3]:…

verilog asic

asked Mar 14 '13 at 19:37

aditya3524

175
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4
12

2

votes

3 answers

How does one find non-conformance to a spec when both the RTL'ers and the verification engineers miss a particular spec feature?

I have some questions regarding IP verification. Suppose if a particular design/functionality from an IP specification is missed both in the RTL and the verification plan (Coverage points), how would you identify this bug? Since it hasn't been…

verilog specman asic

asked Sep 07 '11 at 09:48

Kumar

43
3

2

votes

1 answer

What is maximum size of the Queue in SystemVerilog?

I am writing code to check the pulse width of the clock. I am storing the width of the pulse inside the queue. Since the simulation is going to run for 2 seconds, the size of the queue is going to enormous. I wanted to know what is the maximum size…

system-verilog verification asic

asked Feb 10 '21 at 12:38

afzal junaidi

31
4

2

votes

1 answer

Partial assignment to signal of record type when setting initial value

Is it possible to do partial assignment to a record type on initialization? Something like: type t_foo is record a : integer; b : std_logic; end record; signal bar : t_foo := (b => '0'); In case of a normal signal assignment I could…

vhdl fpga asic

asked Mar 30 '19 at 20:34

andrsmllr

1,231
18
39

2

votes

1 answer

Extreme pipelining in VHDL?

I was wondering which of the following designs is faster, i.e., can operate at a higher Fmax: -- Pipelined if crd_h = scan_end_h(vt)-1 then rst_h <= '1'; end if; if crd_v = scan_end_v(vt) then rst_v <= '1'; end if; …

vhdl fpga mux pipelining asic

asked Feb 13 '17 at 09:30

Ran

31
3

2

votes

2 answers

How can I use $display statement within sequence block, to display some info in System Verilog Assertions (SVAs)?

I want sequence blocks to display some information, while they are being executed. e.g.: sequence A; a; $display ("Signal A asserted here"); endsequence I tried this code, but encountered the following error: Task $display is invoked where…

system-verilog vlsi asic system-verilog-assertions

asked Feb 02 '17 at 17:51

Anand

363
5
11

2

votes

1 answer

Bit width different in verilog

What is different between {a + b} and (a + b) in verilog. I used the simulation to do: reg [3:0] a = 4'b0001; reg [3:0] b = 4'b1111; reg [4:0] c = (a + b); give the result c = 5'b1_0000 but reg [4:0] c = {a + b}; give c = 5'b0_0000; It means the…

verilog fpga asic

asked Sep 16 '16 at 15:39

Thang Nguyen Toan

39
1
2

2

votes

2 answers

Clock Domain Crossing for Pulse and Level Signal

For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?

verilog cdc asic digital-design

asked Jun 28 '16 at 04:57

Ishita Shah

99
1
4
12

2

votes

3 answers

What does "quality of result (QoR)" cover?

The vendors of EDA tools for HDL design and simulation are increasingly using the term quality of result (QoR). Especially when it comes to high level synthesis (HLS) for FPGAs the term is used in inflationary numbers, without prior definition. But…

vhdl verilog fpga hdl asic

asked Mar 27 '16 at 18:51

andrsmllr

1,231
18
39

2

votes

1 answer

What is the implication of not resetting a register in reset aware always_ff block?

What is the consequence of not resetting a flop inside a reset aware alaways_ff block? Example 1: always_ff @(posedge clk, negedge rst) begin if (~rst) begin reg_a <='0; reg_b <='0; end else begin if (condition_1) begin …

system-verilog register-transfer-level asic

asked Feb 06 '16 at 02:41

newbie

4,639
10
32
45

2

votes

3 answers

What is the exact criteria for an inout port, when sometimes inout and output ports can be interchangeably used in Verilog?

In the below module, ideally cnt, width & start should be inout port, instead of output port. But I tried with those ports as output ports and still I am able to run it without any error. So can inout and output ports be used interchangeably in…

verilog fpga system-verilog asic

asked Dec 12 '15 at 12:52

Karan Shah

1,912
1
29
42

2

votes

1 answer

OpenCL (or Other) Programming for ASIC devices?

I've recently learned some of the tools of GPGPU and parallel programming (OpenCL, CUDA, C++ AMP, and OpenMP) and have been looking for more things to tinker with. I know that there are purpose-built USB ASIC devices for fast bitcoin mining ("block…

c++ c opencl asic

asked Sep 08 '13 at 07:29

Jason Champion

2,670
4
35
55

2

votes

1 answer

TAP (Test Anything Protocol) module for Verilog or SystemVerilog

Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting…

verilog fpga tap system-verilog asic

asked Oct 08 '09 at 20:20

Brian Carlton

7,545
5
38
47

2

votes

1 answer

Do any hardware (ASIC) companies use mercurial (hg)

Do you know of any large companies (preferably hardware) successfully using mercurial as their version control system (vcs.) I have experience with svn/cvs/perforce and a little git. Internal politics is pushing us toward cvs, although I feel this…

svn mercurial hardware cvs asic

asked Jun 22 '12 at 19:56

user929821

23
2

Questions tagged [asic]