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I am trying to make a counter that depends on a signal. The signal is high for two cycles and low for next two and this continues till the end. During the high pulse, count should start from 0, 1 . When the pulse is low count is 'x and from next high it continues from 2, 3 then again 'x for two cycles (upcounts only when pulse is high) and then again 4, 5. I am new to Verilog and this is an assignment.

When I made the following code I am getting counts 1 2 x 1 2 x always. Any help?

always@(posedge clk or posedge rst)
If(rst)
Count <= 0;
else 
Count <= signal; 

assign signal  = pulse ? Count + 1: 'x;

I am getting 1 2 x x1 2 x x instead of. 1 2 x x 3 4 x x 5 6 x x etc. Any help is appreciated.

s.21
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2 Answers2

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You just need to make the count register wider. Right now, it's only one bit so it rolls over once you get to (1 + 1 = ) 2. If you make it wider, it will be able to store the state.

dustinwerran
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  • Hello thanks for the reply . The vector is already 16 bits wide . I have written hex . Let me tell you what I am trying to do . If I get data in the sequence 1 2 x x 3 4 x x 5 6 x x etc .they are the depth of memory containing data . I want to pop data from this counter values . I am getting 0001 0002 x x 0001 0002 x x which are hex (16 bits) with above code . – s.21 Sep 02 '18 at 15:22
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When you assign signal to x, count will pick up that value on the next clock cycle. Then, when pulse goes high and signal becomes known, it will assume x means zero and add one to it, so the output will be one. Then, the next cycle, output will be two. What you need to do is preserve the state rather than resetting it. Try adding if (pulse) before count <= signal.

dustinwerran
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  • Hello , thank you that did solved the problem and now I am getting the values as I needed . Now the problem is by writing the signal in else if (signal) I have created a latch which will not be synthesizable . So I was using assign . When I remove else if which you suggested I am not getting any counters. . waveforms show x . Can you improve your suggestion so that I do not get a latch and get a flop during synthesis . Thanks for earlier replies – s.21 Sep 02 '18 at 16:09
  • Latches are synthesizable. If you want to implement a flip flop instead of a latch, just use always_ff. – dustinwerran Sep 02 '18 at 17:03
  • Yes . I wasn't aware of that . Thank you. I am getting perfect counter – s.21 Sep 03 '18 at 12:12