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Questions tagged [asic]

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a specific application, rather than being a general-purpose IC.

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a specific application, rather than being a general-purpose IC.

See Wikipedia page on ASICs.

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Look-Up Table division synthesizable in an ASIC/FPGA design? Makes any sense?

I was studying the ways to make an efficient FPGA project (toward to become an ASIC design) which include division operations of simple 32 bits binary numbers. I have found that the most expedite way to do it, is using LUT (Look-up table), than…
sujeto1
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Comparing simulation performance

Which of these hinders the simulation performance in my testbench and why (Looking for an answer from system verilog compiler perspective): task A; wait(dut_if.a==1); . . endtask OR task A; forever @(posedge clk) begin if(dut_if.a==1).. …
Omkar Manjunath
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timing analysis report for ASIC synthesis

I am having some problems in getting a pre place&routing timing analysis report for ASIC synthesis to get timing we should use ABC in the flowing steps: 1-­strash­-Transforms the current network into an AIG(graph with two logic gate…
Ebraheem Kashkoush
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how to write a restore reset formal test which has a long timing

I used to verify a module that consists of a serial port with a set of registers by dynamic tests. One of the test is a restore reset test. The timing sequence is (i) write a random data into a register from serial port (took 40 clock cycles) (ii)…
TyL
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Compilation error: A net is not a legal lvalue in this context

I am a newbie to Verilog and had a problem while defining a if-else loop. The error message is A net is not a legal lvalue in this context" for all assign statements in the given code. always @(adbar) if (adbar==1'b1) begin assign…
Envyh121
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synthesizable asynchronous fifo design towards an FPGA

I need some advice on how to design an asynchronous FIFO. I understand the meta stability issue when capturing data into a different clock domain, my question is how does using a two flip flop shift register assist in synchronization of write…
Vamsi
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is design compiler& encounter is for ASIC design and quartus&modelsim is for FPGA design?

Right now, I am trying on place-routing on encounter, but when I search on web, I always see the tuition about quartus routing. For curious, I try to find out the difference between two of them. However, there is not any exact answer right now. But…
user3443629
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Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

I am synthesizing some multiplication units in verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using booth encoding when multplying or if you just use the * symbol and let…
Veridian
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Cannot find function for these actuals

My compiler is giving me these errors: # Error: COMP96_0305: SUBONE_MODULE_VHDL.vhd : (93, 23): Cannot find function "TO_INTEGER" for these actuals. # Error: COMP96_0138: SUBONE_MODULE_VHDL.vhd : (93, 23): The index types in the reference to the…
trayres
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RTL simulation vs Delta cycle simulation

Could some one please elaborate on ​"RTL simulation is faster than delta-cycle simulation but can not be used in all situations"? I don't know what Delta cycle simulation
chitranna
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Image-processing ASIC

A video-camera is mounted opposite a blackboard on which several concentric circles are roughly drawn in chalk. The circles are non-ideal, and the camera is not quite steady. The camera has a CVBS (composite) output. I need to make a…
Igor R.
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How to generate PREADY signal from slave in APB protocol?

I am designing AMBA APB slave. All signals for AMBA APB in my design are being generated properly from master side but in what case my slave should generate PREADY signal? PENABLE, PSEL, PADDR and PDATA are avalible from master. When should my slave…
Payal
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How to generate a .db file from TSMC 65nm Standard Cell Library？

I have been using TSMC 180nm Standard Cell Library before and here is its directory structure： In the directory of synopsys, things are as followers: The file slow.db is used to synthesize the RTL Verilog in Design Compiler. Now,I got a TSMC 65nm…
chaotetung
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What type of asynchronous reset for flop is better ? active low or active high

Active Low Reset always @(posedge clk or negedge rst_n_i) if(!rst_n_i) out <= 'd0; else out <= out + 1'b1; Active High Reset always @(posedge clk or posedge rst_i) if(rst_i) out <= 'd0; else out <= out + 1'b1; In an FPGA this…
arun
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How to do matrix multiplication in Verilog?

I am trying to multiply 1x3 * 3X64 matrix, here since each value in matrix is decimal number so for each value I have taken 4 bits that is 4x64 bits in total accessing 4bits of each row at a time. I tried to generalize it. The matrix is of form 1x3…
Swaroop
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