-5

Question:

How do Hardware languages (HDLs) differ from general purpose languages such as Python, Java, etc. In particular, what is the primary trade-off that causes general purpose languages to be sub-optimal for FPGA's when compared to VHDL and Verilog?

Context:

I'm a programmer but definitely work at a high level of abstraction such as JavaScript, tinkering with API's, etc. My low-level knowledge is very limited but I am playing around with an FPGA and have some novice questions that I cannot solve with Google or Wikis.

Considering I am a novice, please do not vote harshly against this post. Just state your suggestions for the question and I will happily revise! :)

Example:

For example, why isn't everyone just coding FPGAs and ASICs with Python or C# instead of Verilog or VHDL? I understand that there are some Python libraries, but I have read that they are limited in their viable use-cases. I would greatly appreciate someone shining some light on why HDLs are necessary and beneficial and why general purpose languages are not optimal in comparison for these scenarios.

Thanks in advance!

Tucker
  • 367
  • 1
  • 3
  • 11

1 Answers1

2

This is a broad opinionated question, but I think there is a short answer. In some sense, they are all programming languages, i.e text descriptions that gets compiled into a set of machine instructions to be executed on a host machine(software). But an HDL is also a text description that gets compiled into a set of machine instructions to build another machine (hardware).

Technically, any programming language could be used to describe hardware (SystemC in C++ as an example), Verilog and VHDL were specifically developed to model and simulate hardware most efficiently.

dave_59
  • 39,096
  • 3
  • 24
  • 63
  • 1
    For extremely broad definitions of "machine instructions"... Using that term to describe something derived from HDL might be unnecessarily misleading. – fru1tbat Aug 23 '16 at 20:12