Highest Voted 'asic' Questions

1

vote

0 answers

Yosys : Is it possible to generate " Gate-level constraints file" using Yosys. That is like sdc file generated by Synopsys RTL compiler

Yosys: I am new to Yosys. But I am familiar with the RTL compiler. I am able synthesis modules using yosys. Is it possible to generate " Gate-level constraints file" using Yosys. That is like sdc file generated by Synopsys RTL compiler.

asic yosys

asked May 26 '16 at 22:33

Sudheer Vaddi

11
1

1

vote

3 answers

What's the advantage of bit over reg in systemverilog?

Variables in testbench mostly are instantiated as bit rather than reg. But bit is just 2 state variable (0 and 1), reg is 4 state variable (0,1,x and z). Why people used bit as testbench variables? I took over an old project and all the testbench…

system-verilog verification asic test-bench

asked Apr 25 '16 at 11:24

TyL

84
9

1

vote

1 answer

timing for ASIC design, proper clocking for an D/A

I am making my first ASIC and I am having trouble understanding something. I have an internal clock of 80MHz that appears on a pin of the ASIC, the other pins include the data output pins connected to the D/A. All the traces on this particular board…

clock timing asic

asked Mar 21 '16 at 18:39

woshidon

13
2

1

vote

0 answers

Efficient synthesizable way to read inputs of variable length in one simulation

I am new to vhdl and I have a question that I could not find an answer to. I am trying to implement some algorithm that operates on a vector 1024 bits long. So I have to read data from a file and insert them in this temp_vector(1023 downto 0). The…

vhdl fpga asic

asked Nov 12 '15 at 17:48

thodmir

11
1

1

vote

1 answer

Divide by 2 clock and corresponding reset generation

My question is about using generate a synthesizable divide by 2 clock and corresponding reset in verilog. We can generate a divide by 2 clock as below using verilog module frquency_divider_by2( input rst_n, input clk_rx, output reg…

verilog reset clock synthesis asic

asked Jun 15 '15 at 06:26

srikanth

23
4

1

vote

1 answer

Adding skew to improve timing

I want to improve the operating frequency of my design, In the register to register timing analysis I have observed a lot of delay in the combinational elements. This is impacting the timing of the circuit and the slack observed is about -0.3ns , I…

verilog fpga system-verilog register-transfer-level asic

asked May 24 '15 at 09:00

Vamsi

13
4

1

vote

2 answers

Synopsys Design Compiler and PrimeTime timing analysis report remain same

I had done the timing analysis of a counter in both Synopsys Design Compiler and PrimeTime, but got the same output! Any problem ? Then how PrimeTime timing analysis will become more accurate than DC? Design file used is counter.v and is given…

verilog synthesis asic

asked Mar 21 '15 at 02:34

Jithin

88
1
12

1

vote

1 answer

What if I used Asynchronous reset, Should I have to make as synchronous turned it?

At we make IC( I mean physical design in Hardware). As i know, the input reset is always Asynchronous. I wonder that What if I used Asynchronous reset, Should I have to make into synchronous? or Can we just used asynchronous reset?

vlsi asic

asked Feb 07 '15 at 11:45

BONGKA

107
1
6

1

vote

0 answers

Efficient mapping of hardware I/O space into Linux virtual space

I am working on an SoC with an embedded ARM and lots of hard-wired IP blocks. Each hardware block is memory mapped into the ARM space, i.e., the registers to control the hardware block is in the space 32-bit address space of the ARM CPU. We have…

c linux hardware mmap asic

asked Oct 28 '14 at 19:20

guraaf

163
4
12

1

vote

3 answers

Store std_logic bits in ascending order into a large array

I have an array of 2048-bits and i would want to store the incoming bits from 0 - 2047 in ascending bit order as it comes in FPGA on each rising edge of the clock cycle. Eg: array[0] <= 1st bit array[1] <= 2nd bit ... .. array[2047] <= 2048 th…

vhdl verilog fpga synthesis asic

asked Jan 03 '14 at 13:25

powernest

261
1
2
12

1

vote

2 answers

Using an ASIC to brute force MD5

Is it possible to use an Application Specific Integrated Circuit (ASIC) to brute force MD5 hashes and thus reverse them down to their original form? I know there could be multiple collisions, but leaving that aside, would it be possible? The idea…

hash md5 brute-force asic

asked Dec 14 '13 at 16:35

Spencer D

3,376
2
27
43

0

votes

1 answer

STA of 2 clocks with the same frequency

Imagine a design has 2 input clocks. They have the "same" nominal frequency but originate from 2 different sources and therefore are asynchronous to each other. The clocks are defined as follows: create_clock -name {clock_a} -period 10.000 -waveform…

fpga vlsi asic

asked Mar 22 '23 at 22:01

shaiko

159
6

0

votes

2 answers

Where does the third dimension (as in 4x4x4) of tensor cores come from?

As I understand, the Nvidia tensor cores multiplies two 4x4 matrices and adds the result to a third matrix. Multiplying two 4x4 matrices produces a 4x4 matrix, and adding two 4x4 matrices produces a 4x4 matrix. Still "Each Tensor Core provides a…

matrix gpu core asic

asked Jul 10 '22 at 21:53

Alfred

5
4

0

votes

2 answers

SystemVerilog Assertion does not fail when it should

I have a simple assertion as follows: $rose(req) |=> !req[*1:10] until ack ##1 !ack; As I understand, on detection of $rose(req), the assertion should check for !req to be low consecutively for max 10 clocks OR -until- ack arrives (ack=1). Once ack…

fpga register-transfer-level system-verilog-assertions asic

asked Jun 22 '22 at 17:14

CCRCCR

19
2

0

votes

1 answer

SystemVerilog : Port connection based on parameter

I'm trying to instantiate multiple copies of a module using a generate. However, these multiple copies have a different output type (depending on a parameter). Is there a way to conditionally connect an output port. eg: module #(parameter type…

verilog system-verilog hdl asic

asked Jun 10 '22 at 17:51

Wynn

19
1

Questions tagged [asic]