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I've been getting a cross-module resolution error, when the compiler expands the definition as follow:

in file, say path_defines.vh (where the definitions is at):

`define apple aaaa.bbbb.cccc.\pie[0] .dddd.eeee

I'm using the "\" character accompanied by a tailing "white-space" to escape the characters "[" and "]" as defined in the 2012 verilog manual.

So when the compiler parses a file(say eg: design.vs) with the defined term as seen here :

`apple.ffff.gggg

and tries to expand the definition, the compiler gives me a :

Cross-module reference resolution error.

Error found while trying to resolve cross-module reference.

TheSprintingEngineer
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  • it tells you that the signal does not exist. apparently you have a bug in your path. Besides, why exactly do you use the 'escape name'? the compiler does not generate those. I do not think that you need it there. – Serge Jul 03 '17 at 01:53
  • Since I used the "[]" characters in the definition names, I need to use the "\" and a tailing white space to escape the "[]" characters – TheSprintingEngineer Jul 03 '17 at 02:03
  • perhaps i should clarify, would the Synopsys DC compiler have a problem with escape characters ? – TheSprintingEngineer Jul 11 '17 at 02:23

1 Answers1

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If your example is similar to the below, you do not need any escape name. The compiler will understand pie[0] as a part of the name. [] are ok there. 

module top;
    aaa aaa();       
    assign aaa.bbb.pie[0].ccc.ddd = 0;
endmodule
module aaa();
    bbb bbb();
endmodule 
module bbb;
    generate
      for (i = 0; i < 2; i++) begin: pie
         ccc ccc();
      end
   endgenerate
endmodule // bbb
module ccc;
   wire ddd;
endmodule
Serge
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