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I am trying to use Yosys to implement post-synthesis manipulation of connections. i.e, I want to manually manipulate the connections between verilog modules after the synthesis pass is done.

I tried investigating the code for a while, and I found out that I need to create a subclass of the "Pass" structure that implements the exact feature I need.

I need to find out how to manipulate the connections themselves. So, i need to know whether or not the "Design" structure is the one that contains the representation of the Verilog design that is used as an input to the tool. In case this is true, where exactly can I find the connections (which variables are used to represent the connections)?

Also, if I need to automate the manipulation of connections, I need to know how the tool assigns specific names to each connection, so that I would be able to implement an automation algorithm that can automatically choose specific connections to remove, or add new connections, based on the names of the existing connections. By the names of connections, I mean the names that are displayed by Yosys in case GraphViz is used to present the design graphically.

Thanks in advance. Best Regards

AbdelAziz
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1 Answers1

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where exactly can I find the connections (which variables are used to represent the connections)?

If two module ports are connected to the same net, or two nets that are connected to each other (Module::connections()), then the ports are connected.

The SigMap class can help you dealing with the case of wires connected to each other.

I need to know how the tool assigns specific names to each connection

Connections don't have names.

Wires have names. Their names either come from the HDL design or are auto generated (in most cases by use of the NEW_ID macro).

If you need to guess the name of an automatically generated wire then you are definitely doing something wrong. Unfortunately you don't describe what exactly you are trying to do and why you think you have to guess the names of automatically generated wires, so I can't tell you what it is you are doing wrong..

Make sure you have read and understood the CodingReadme file, the examples in examples/cxx-api/, and the presentation slides dealing with the Yosys API (at the end of that slide deck).

CliffordVienna
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  • I am trying to traverse the circuit, and selectively remove some specific connections such that the ports are still there, but they are no longer connected to each other. i.e, if the design contains an AND gate whose output is connected to one of the inputs of an OR gate, I would like to remove the wire connecting them. It might not be necessary to know the generated names of the wires for this, but I need to traverse the whole design, and remove some wires based on specific conditions. – AbdelAziz Oct 14 '17 at 11:32