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For https://i.imgur.com/NCUjYmr.png , why doesn't the signal "reset" assumed to be '1' initially ? Anyone have any idea why the assume does not work ?

kevin
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  • looks like those assumptions are for formal verification, not for simulation. So, presumably they are used by the tool to set up assumptions about the initial state. – Serge Dec 18 '17 at 11:58

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I found the solution. I am in temporal induction where it starts at a state which is not the initial state of the system. Therefore, the signal "reset" is not assumed to be '1' initially

kevin
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Assumes will work as assumptions only in formal verification environment. But in simulation based verification, they work as an assert statement only.

As per the LRM :

The immediate assume statement specifies that its expression is assumed to hold. For example, immediate assume statements can be used with formal verification tools to specify assumptions on design inputs that constrain the verification computation. When used in this way, they specify the expected behavior of the environment of the design as opposed to that of the design itself. In simulation, an immediate assume may behave as an immediate assert to verify that the environment behaves as assumed. A simulation tool shall provide the capability to check the immediate assume statement in this way.

Due to this, in your design, it won't actually assume the value, but it will check whether the proper value is given or not.

Karan Shah
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