how to decompose a circuit into high-level modules

Question

I am interested in taking a circuit, described in logic, and decomposing it into high-level connected modules, where each module say has 6 inputs and 5 outputs max. So it is similar to FPGAs in some sense except that the modules could have multiple outputs, and they do not need to implemented as LUTs. I plan to optimize the logic of these modules separately. How can I do that?

Answer 1

So you would like to partition your circuit into small circuits with max 6 inputs and max 5 outputs. There is no existing functionality in Yosys or ABC to do that. (ABC is the tool that is used for most of the low-level logic optimization within Yosys.)

You could attempt to write a pass for that (there is a lot literature on graph partitioning algorithms and I'm sure there is something that would work reasonably), however there is a fundamental problem with your requirements imo:

Obviously it would be very simple to e.g. partition any logic into cells with say 6 inputs and 3 outputs: Simply map the logic to 2-input gates and then randomly pack 3 of those gates into one cell. This would be a valid partitioning, but it would not be a very useful partitioning because each of the outputs depends on different inputs. A partitioning will only be useful when at least some of the inputs are shared among the outputs of the cell. And this is where the problem is: You will find that in almost all real-world circuits only very few signals can be shared in this way and that even with a perfect partitioning algorithm your cells will either contain mostly independent outputs or have only a very small number of outputs.

I don't know exactly what your application is, but one simple approach can be to e.g. first simply map the entire circuit to say 4-LUTs and then have a simple pass that detects 4-LUTs that share some inputs and merge up to three of them (if they share enough inputs so that together they have a maximum of 6 inputs). But I'm afraid that you will find that only a small number of 4-LUTs would be share-able that way.