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I am learning verilog, trying do make the "hello world" in the VGA world (a bouncing ball) on a ice40LX1K board (olimex ice40HX1K + VGA I/O board).

I have a strange problem: when I simulate my design using iverilog + GTKWave, it seams to work good. But the implementation in hardware does not work.

What is strange is that in the hardware implemention, the ball is doesn't move .. and its position is all zero (0,0) althou the verilog code never should set it overthere. It looks like changing the value of xpos_ball or ypos_ball does not actually change these values. (a hardware issue? a yosys issue)? In the iverilog simulation, location of the ball does change as expected.

I have no idea if this is a error in my own verilog code (as I am new in this, this is very well possible), an issue in yosys, or a problem in the hardware (speed issue, is the 100 Mhz clock to fast?) or something else?

Any proposals on how to troubleshoot this, or next steps for this kind of issue? Are there other debugging-tricks I can use?

(edit: link to the actual verilog-code removed as not relevant anymore)

Kristoff

kristoff
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1 Answers1

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is the 100 Mhz clock to fast?

Yes. That design is good for 39.67 MHz:

$ make vga_bounceball.rpt
icetime -d hx1k -mtr vga_bounceball.rpt vga_bounceball.asc
// Reading input .asc file..
// Reading 1k chipdb file..
// Creating timing netlist..
// Timing estimate: 25.21 ns (39.67 MHz)

Edit re comment:

You can always safely divide a clock by a power of two by using FFs as clock dividers:

input clk_100MHz;

reg clk_50MHz = 0; // initialization needed for simulation
reg clk_25MHz = 0;

always @(posedge clk_100MHz) clk_50MHz <= !clk_50MHz;
always @(posedge clk_50MHz) clk_25MHz <= !clk_25MHz;

(A non-power-of-two prescaler is not always safe without making sure with timing analysis that the prescaler itself can run in the high frequency domain.)

CliffordVienna
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  • Hi Clifford. OK. Thanks. What would then the best way to solve this? The olimex board has a fixed 100 Mhz clock and the iCE40HX1K-VQ100 does not have a sysclock PLL so I am stuck with the 100 Mhz clock. Does creating a 25 Mhz clock in verilog help? Or is this still "running at 100 Mhz"? Kristoff – kristoff May 21 '17 at 20:05
  • Clifford thanks! When starting out with VHDL on a xilinx and a altera board, I was told that one should **never** use a `if rising_edge(some-REGISTER)` (i.e. not the clock signal itself). The reason being "clock-signals are routed in a special way on the FPGA as they need to arrive at all modules in the same time. ... This is **only** so for clock-signals, not for other signals". Can I conclude that -as long as the division is by a power-of-two- it **IS** safe to do this anyway. Or is this specific to the lattice chips or yosys? Kristoff – kristoff May 22 '17 at 19:13
  • @kristoff Yes. The reason is that in this case the intermediate signals are routed to ONLY ONE flip-flop, so there is no need for length matching. The final clk_25MHz clock will be routed automatically over a global clock buffer by arachne-pnr. If you want to be explicit about it you can manually instantiate a SB_GB cell for that if you want, but that's just a matter of coding style since arachne-pnr should be smart enough to do that for you anyways. – CliffordVienna May 22 '17 at 19:20
  • Vielen Dank!!! Very helpfull and very interesting information on how fpga routing-software works internally! :-) – kristoff May 22 '17 at 19:34