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I am new to the world of FPGAs besides a course in undergrad using an Altera training board, but I've recently been assigned to do some work with a Xilinx Nexys Video A7 FPGA. Since this project involves updating firmware, my first task is to download the existing program that is currently on the FPGA. However, I can't find anything online that describes how to do so.

Can one even extract the behavior from an FPGA into a VHDL program, or does it only go one way? I find it hard to conceptualize turning hardware back into HDL unless the HDL itself gets stored somewhere on the board upon upload.

Again, I'm quite new to the FPGA world, so sorry if this is a dumb question. Thank you for your help.

tyler_bowlcut
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Reverse engineering the HDL from the bitstream (what the binary file that is used to configure the FPGA is called) is an extremely difficult task, possibly even an impossible one.

You could possibly extract a netlist (the circuit schematic at the cell level), which would essentially give you how all the logic elements are connected on the FPGA. From there you would need to rebuild the actual hardware, which is extremely difficult (see this paper, which goes into the required steps and their complexity for hardware reverse engineering).

In your case, if your current bitstream was generated inside the company, there should be at least some documentation if the source is no longer available.

If it is a design that was purchased, I would try to get the original design and work from there.

Otherwise, you are out of luck and will need to re-create a new design.

Simon Doppler
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