template error in Xilinx

Question

I have written a program in xilinx, this code compiles fine in ModelSim but I get this error when I compile it in xilinx.

ERROR:Xst:899 - line 78: The logic for <iterator> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

I don't know why I am getting this error. Here is the code:

module BcdCounter( input clk,input reset, output reg [3:0]out
);

reg [23:0]iterator;

always @(posedge clk,negedge reset)
begin

if(~reset)
begin

out=0;
iterator=0;

end

else
// clock divider
if(iterator==50000000) // 50Mhz clock divider
begin

out<=out+1;
iterator=0;

end

iterator=iterator+1;

end


endmodule

Regards

You are mixing blocking and non-blocking assignments. That may have something to do with it. — dwikle, Mar 02 '13 at 13:59
Iterator=iterator+1 is not in an else clause, is likely only working in model sim because blocking assignments have been used. Iterator = 0, would not get executed in hardware. — Morgan, Mar 02 '13 at 14:14
whether I use blocking or non blocking statements for `iterator` I always get this error — James Aflred, Mar 02 '13 at 14:33

Brian Magnuson · Answer 1 · 2013-03-02T23:32:10.000

Three (five) things I notice:

1) I would use 'or' instead of a comma to separate 'clk' and 'reset' in your always@ statement

2) In real clocked logic you should always use blocking assignments for anything you're expecting to infer flops. Blocking assignments should only be used for temporary variables.

3) You're mixing blocking and non-blocking assignments to 'out'. That is a definite no-no.

4) Your increment of iterator is outside of the reset if/else which will really throw a spanner in things.

5) As an aside please indent your blocks. It's very hard to tell what lines are associated with what block with everything left justified.

module BcdCounter (
   input            clk,
   input            reset,
   output reg [3:0] out
);

reg [23:0] iterator;

always @(posedge clk or negedge reset) begin
   if(!reset) begin
      out      <= 0;
      iterator <= 0;
   end else begin
      // 50MHz clock divider
      if (iterator == 50000000) begin
         out      <= out + 1;
         iterator <= 0;
      end else begin
         iterator <= iterator + 1;
      end
   end
end

endmodule

so where can I increment the iterator for removing this error — James Aflred, Mar 02 '13 at 17:39
By making the 'else' portion of the reset statement include the increment step if 'iterator' isn't turning over. Answer edited to include code and stylistic fixes. — Brian Magnuson, Mar 02 '13 at 23:33
The code will not run properly unless the range is increased for `iterator`. `50000000` requires at least 26-bits and `iterator` only has 24-bits. — Greg, Mar 05 '13 at 02:07

template error in Xilinx

1 Answers1