How do I rewrite this VHDL code to prevent latches?

Question

architecture Behavioral of REGISTERS is

type REG_FILE_TYPE is array(0 to 15) of STD_LOGIC_VECTOR(15 downto 0);


signal REG_ARRAY : REG_FILE_TYPE:= (others => X"0000");
begin
process(WRITE_ENABLE,REG_CLOCK) is
 begin  
 
    case (WRITE_ENABLE) is
        when '1' => REG_ARRAY(to_integer(unsigned(WRITE_ADDRESS))) <= REG_INPUT;
        when '0' => NULL;
        when others => NULL;
    end case;
    
end process;

you have `REG_CLK` in the sensitivity list, but is not used in the process. Also `WRITE_ADDRESS` and `REG_INPUT` are missing. To avoid latches the process either needs to be synchronous or signals must be explicitly assigned in ALL branches. — Tricky, May 19 '21 at 19:26
IEEE Std 1076.6-2004 RTL Synthesis (withdrawn) 6.4 Combinational logic "For combinational logic, the process sensitivity list shall list all signals read within the process statement." — , May 20 '21 at 00:18
Welcome to StackOverflow! Please take the [tour] and read "[ask]" to learn how this site works. -- Please [edit] your question and correct your source formatting. — the busybee, May 20 '21 at 06:41

score 0 · Accepted Answer · answered May 21 '21 at 12:28

You forgot to add the clock to the process. If there's no clock, and the synthesizer infers that you have a need some memory for the implementation, then it has no other option than to add latches. This is almost always a mistake.

Besides that, I don't like your case structure here, where a simple if-then would do. This is how I'd implement it:

process(REG_CLOCK) is
  begin  
    if rising_edge(REG_CLOCK) then
      if WRITE_ENABLE = '0' then
        REG_ARRAY(to_integer(unsigned(WRITE_ADDRESS))) <= REG_INPUT;
      end if;
    end if:
end process;

How do I rewrite this VHDL code to prevent latches?

1 Answers1