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We use after [some delay] statement for providing delay and that we can analysis in simulation. But when we will load this model in to FPGA so in actual hardware being made by VHDL code will have affect of delay or this delay is limited to simulation only?

a <=   not b after 1s;

So suppose I connected one switch to b and LED to a so will I get one second delay in between pressing the switch and updating LED status?

Paebbels
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Neil Terminator
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    that would be `after 1 sec;` –  Aug 25 '16 at 09:33
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    What hardware do you suppose your synthsiser would generate to implement `a <= not b after 1s;` ? – Matthew Taylor Aug 25 '16 at 14:10
  • i seen hardware after synthases and it generated only not of b connected to a; – Neil Terminator Aug 25 '16 at 15:12
  • Exactly. So, surely if you were going to design a logic circuit to implement a delay of 1 second, you'd be needing flip-flops and some kind of clock, would you not? My point is when you code in VHDL, you are designing hardware and need to think about what hardware is going to be required to implement the functionality you require. Just saying `after 1 s` doesn't give the synthesiser enough detail to work with; you need to design (ie code up) a circuit with a clock and some flip-flops. – Matthew Taylor Aug 25 '16 at 15:25
  • i got your point so VHDL language and its construct are found to have two role one is in simulation as well as synthases?. like i am working on C language so it has one role and that to generate assembly and from that executable for target device but in case of VHDL ,it contains keywords and other constructs too for simulation as well as for describing hardware i.e synthesis am i right ? – Neil Terminator Aug 25 '16 at 15:33

2 Answers2

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as said before, the wait statement cannot be synthesized and will only affect the simulation. However, I should add that even in simulation you might not get what you expect. Allow me to explain.

VHDL offers 2 delay models: transport delay and inertial delay, the latter being the default, which you selected by not specifying which model to use.

If b would happen not to be stable in the course of the delay, say it toggles every 500ms, a would not toggle as you may desire. To really introduce pure delay, select the transport delay model as follows:

a <=  transport not b after 1s;

Of course, again, this cannot be synthesized and is for simulation purposes only.

chrisvp
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When you are simulating you need to provide when things happen and what happens to the inputs. After implementing it on the FPGA, exterior events create the inputs and the simulation has nothing to do about it.

So if I understood your question right, yes, the delay you are showing will only affect the simulation.

EDIT : Regarding the timer, you know the FPGA's clock frequency. So you can create a variable and increment it on each clk_up (I use CLK = '1' and CLK'Event but there are better ways to do it), and when it reaches the same value as the clock frequency, 1 sec has passed.

Not-so-Pseudo code:

signal clock: unsigned (9 downto 0);
if CLK = '1' and CLK'Event then
   clock<= clock + 1;
   if clock = "1100100000" then --clock frequency (this is an example)
       clock <= "0000000000"
       -- 1 secound passed!
   end if;
end if;
Syphirint
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