What does the PINNAME to PINNAME data path in Xilinx ISE synthesis timing report mean?

Question

I've written a simple DFF with the following VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFF is
    port (d: in  STD_LOGIC;
          q: out  STD_LOGIC;
          clk: in  STD_LOGIC;
          reset: in  STD_LOGIC);
end DFF;

architecture Behavioral of DFF is
begin
    process (reset, clk) begin
        if (reset = '1') then 
            q <= '0';
        elsif (rising_edge(clk)) then 
            q <= d;
        end if;
    end process;
end Behavioral;

I subsequently run simulation and synthesis. When I examine the synthesis report, in the Timing Report section, this is present:

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.597ns (Levels of Logic = 1)
  Source:            q (FF)
  Destination:       q (PAD)
  Source Clock:      clk rising

  Data Path: q to q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.447   0.579  q (q_OBUF)
     OBUF:I->O                 2.571          q_OBUF (q)
    ----------------------------------------
    Total                      3.597ns (3.018ns logic, 0.579ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================

What does the q to q data path signify, and what does it even mean?