Why am I getting a High Z output for cathode in seven segment display controller instead of a numeric value?

Question

I wrote a verilog code for a seven segment display controller as part of my assignment, but in the simulation, i get the following error:

Can someone please resolve this issue? I have attached the following verilog modules:

1.Main controller code

module top(switch, button,clk,anode,cathode);
input wire clk;
input wire[7:0] switch;
input wire[3:0] button;
output wire [3:0] anode;
output wire [7:0] cathode;
wire refreshclock;
wire[1:0] refreshcounter;
wire[3:0] MUXED_digit;

//to instantiate clockmodule here, do this..
clock_module refreshclock_generator (.clk(clk), .sclk(refreshclock));

//to instantaiate seven segment controller modules..

refresh_counter R1 (.refreshclock(refreshclock), .refreshcounter(refreshcounter));
anode_control A1 ( .refreshcounter(refreshcounter), .anode(anode));
bcd_control B1( .digit1(switch[3:0]), .digit2(switch[7:4]),.digit3(button[3:0]), .digit4(button[3:0]),.refreshcounter(refreshcounter), .MUXED_digit(MUXED_digit));
bcd_7seg_case BS1 (.bcd(bcd), .S(S));


endmodule

2. Clock divider code

   module clock_module(t_count,sclk,rst,en,clk);
   
   parameter n=19;
   parameter Nc=400000;
   input rst;
   input en;
   input clk;
   output reg [n-1:0]t_count;
   output reg sclk;
   
   always@(posedge clk or posedge rst) //on FPGA, clock won't start until rst is also pressed. If rst not pressed, then value of N doesn't go into t_count, so at that moment, t_count would be giving us garbage values
    begin //always begin
   
    if (rst==1)
    begin //rst 1 begin
    //counter will be cleared
        t_count=0;
        sclk=0;
    end //rst 1 end
   
    else
    begin //rst 0 begin
    //counter counts normally
        if(en==1)
        begin
            if(t_count<Nc)
            begin
                t_count=t_count+1;
                sclk=sclk;
   
            end
   
            else
            begin
                t_count=0;
                sclk=~sclk;
            end
        end
   
        else
        begin
        //retains previous values
            t_count=t_count;
            sclk=sclk;
        end
    end //rst 0 end
   
    end   //always end
   endmodule
   

3. Refresh counter code:

     module refresh_counter(refreshclock,refreshcounter);
     input refreshclock;
     output reg[1:0] refreshcounter = 0;
   
   
     always@(posedge refreshclock)
     refreshcounter <= refreshcounter+1;
     endmodule
   

4. Anode control code

       module anode_control(refreshcounter,anode); //we want to make sure each anode is turned on based on each case value of the refresh counter
       input[1:0] refreshcounter;
       output reg[3:0] anode = 0;
   
       always@(refreshcounter)
       begin
          case(refreshcounter)
             2'b00: anode = 4'b1110; //digit 1 on (rightmost)
             2'b01: anode = 4'b1101; //digit 2 on 
             2'b10: anode = 4'b1011; //digit 3 on 
             2'b11: anode = 4'b0111; //digit 4 on (leftmost)
          endcase
        end
        endmodule
   

5. BCD control code:

       module bcd_control(MUXED_digit, refreshcounter,digit1,digit2,digit3,digit4);
       input[3:0] digit1; //rightmost digit (ones)
       input[3:0] digit2;  //tens
       input[3:0] digit3;  //hundreds
       input[3:0] digit4;  //leftmost digit(thousands)
       input[3:0] refreshcounter; //because we are checking for both anode value and displayed value at the same time, and also to make sure both of them are in sync with each other
       /*we are choosing which input digit to display when the corresponding anode is turned on. so we can say that the bcd control acts like a 4to1 mux with refreshcounter as select lines*/
       output reg[3:0] MUXED_digit = 0;
   
       always@(refreshcounter)
       begin
       case(refreshcounter)
         2'd0: MUXED_digit = digit1; //digit 1 on (rightmost)
         2'd1: MUXED_digit= digit2; //digit 2 on 
         2'd2: MUXED_digit = digit3; //digit 3 on 
         2'd3: MUXED_digit = digit4; //digit 4 on (leftmost)
       endcase
      end
     endmodule
   

6. BCD to 7 segment code:

      module bcd_7seg_case(bcd,S);
      input [3:0] bcd; 
      //input cs;
      output reg [6:0]S;
   
      //circuit is sensitive to changes in inputs
      always@(bcd)
      begin
      //if(~cs)
      //S=0'b0000_000;
     //else
     //begin
   
     case(bcd) 
   
     0: S = 7'b1111_110;
     1: S = 7'b0110_000;
     2: S = 7'b1101_101;
     3: S = 7'b1111_001;
     4: S = 7'b0110_011;
     5: S = 7'b1011_011;
     6: S = 7'b1011_111;
     7: S = 7'b1110_000;
     8: S = 7'b1111_111;
     9: S = 7'b1111_011;
    endcase
    end
    endmodule