Highest Voted 'xilinx-ise' Questions

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Failed to map the library when using ISE to simulate a program connected with Modelsim

ERROR: Failed to map the library Reason: couldn't execute "vmap": no such file or directory` I have tried to re-compile the Xilinx library, but failed. Could anyone spare time to give me some help?

asked Jul 23 '20 at 01:11

tranquil

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Multiplexer in vhdl with structural design

I am totally new to VHDL and I want to implement the following MUX for a logical implication S0 => S1 without using other gates. I want to use structural design, but one of my main problems is that I don't understand how to map the ports correctly…

vhdl hardware hdl xilinx-ise hardware-design

asked May 08 '20 at 09:09

Landau

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Generating a waveform with three pulses using FSM?

Hi All I want to generate two waveform or signal(let say mode-1 and mode-2 signal) through FSM each having three pulses let's say P1, P2,and P3. these pulse are of width 0.8us each. for mode-1 P1 and p2 are 2 us apart and p1 and p3 are 8 us apart…

vhdl xilinx-ise

asked Sep 25 '19 at 07:14

DIWAKAR MISHRA

65
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2 answers

force ISE synthesis tool to synthesize a signal

In Xilinx ISE (using VHDL language), I have defined these signals: signal counter : integer range 0 to 24_000_000; signal chTriger : std_logic :='0'; and have written the following code: process_counter: process(clk) begin if ( clk'event and…

fpga xilinx-ise

asked Jan 28 '19 at 09:54

Reflection

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Memory regions not displayed in 'lspci -vv' while using 'AXI bridge for PCI express Gen3.0 subsystem'

We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express'. Initially the command 'lspci -vv' used to show memory regions in…

xilinx pci-e xilinx-ise

asked Nov 26 '18 at 10:29

vineeshvs

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Generate multiple binary files on ISE with different serial number

I want to version all the boards on which I put a version of my FPGA. Each board shall have a different serial number stored in an internal ROM. It's basically a 10 digits number (ie: 0123456789). After generating the binary file , how can I modify…

vhdl fpga xilinx xilinx-ise

asked Jul 09 '18 at 14:55

A. Kieffer

372
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1 answer

Xilinx 14.7 license configuration manager is not running

I have installed Xilinx 14.7 but I'm unable to open its configuration manager even after several trials to put in a license as Xilinx gives me this error: ERROR:Map:258: - A problem was encountered attempting to get the license for this…

xilinx-ise

asked Jun 01 '18 at 19:40

Mary

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How to fix Xst:528 this signal is connected to multiple drivers

I am receiving this error in my code,I think this error arises when we try to assign a variable different values in multiple always blocks,but in my case i am not doing so,but still receiving this error. ERRORS: Multi-source in Unit…

verilog fpga xilinx xilinx-ise

asked May 05 '18 at 03:47

Momil Ijaz

23
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Attributes was ignored by XST and synplify pro

I'm using ISE 14.7 , synplify pro 2013.03 and modelsim 10.2c; now I having a problem about keeping a signal's name after synthesis and place&route in ISE and synplify. I used attribute keep and keep_hierarchy in XST,and syn_keep in synplify pro,but…

vhdl xilinx-ise

asked Apr 17 '18 at 03:02

D.vader

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1 answer

I2c Master testing on FPGA board

I have implemented i2c master code for reading temperature value from temp sensor(slave).i am testing my code on FPGA evolution board.FPGA is Microsemi nano very basic FPGA.How can I test my master without connecting to the slave device?

fpga xilinx i2c xilinx-ise xilinx-edk

asked Mar 19 '18 at 12:46

Kanika Sharma

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1 answer

Mimas V2 Spartan 6 FPGA flash memory issue

I recently bought the FPGA Mimas V2 Spartan 6 FPGA Development Board with DDR SDRAM. I'm working with xilinx ise 14.7, verilog code, when loading the binary file generated by xilinx in the fpga with tool conmimasv2_configuration_tool_windows.exe the…

verilog fpga xilinx-ise

asked Dec 27 '17 at 22:59

CasualCoder

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1 answer

Resetting Preg of Dsp slice in virtex 6 FPGA

Here is the VHDL code where i have used a DSP as a MACC unit (multiply accumulate) using the primitives that are available in language templates. At every 7th clock cycle i am resetting the Preg, when i do that the multiplied output of that cycle is…

vhdl signal-processing xilinx-ise

asked Nov 05 '17 at 07:01

rashmi mahesh

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VHDL: Division with error coding but there are errors in compiling on Quartus II but not on Xilinx ISE

I'm very new to VHDL and I would like to get some help. You see, we were told by our instructor to code the division of binary (by converting the binary to integer first) and if the divisor is zero, then the output error waveform will be displayed…

vhdl integer-division quartus xilinx-ise

asked Aug 18 '17 at 03:25

c2s1

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2 answers

Read after Write Latency in Asynchronous FIFO?

I am trying to interface a module with an asynchronous FIFO generated by the Xilinx CORE Generator. However, I have observed that the data supplied at the input port of AFIFO (although correct) starts appearing on dout after a latency of 6-7 clock…

verilog fpga fifo xilinx-ise

asked Aug 07 '17 at 19:00

Candy

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How do you save wcfg waveform data in Xilinx ISim clock cycle resolution

I have a simulation that takes 4 hours to run and don't want to repeat it when I have to measure timing. Is there a way to save the data so that I can review it on demand.

simulation xilinx-ise

asked Jul 23 '17 at 06:43

newb7777

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Questions tagged [xilinx-ise]