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I have a question regarding Xilinx block-ram files. I am working with a group of people on a project. When one person generates a block ram another group member migrates the block_ram.xco, and block_ram.vhd files into their project, and adds the sources in ISE. For some reason this does not work, and the block ram does not work. Are there any other necessary files or steps I've missed?

Logan
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  • What works for me is adding .xco, .xise, .vhd and .ngc to the project directory and adding only .ngc to ISE sources. Although you may need another file if BRAM has initialization file, not sure on that one. – Jonathan Drolet Mar 21 '15 at 19:23
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    What works for me is ignoring the Coregen mess altogether and simply inferring the memory through VHDL. Initialisation contents can be generated via a function called in the initialisation clause, or via an array aggregate in a (usually auto-generated) VHDL package. –  Mar 21 '15 at 23:05
  • Do you use pre-initialized BlockRAMs? If no: @BrianDrummond 's way is very good. If yes: Instantiate the BlockRAMs manually and use a memory mapping file (*.bmm) and the tool data2mem to generate the BlockRAM contents. This tool can also be used to patch bit files with new BlockRAM contents -> no new synthesis is needed. – Paebbels Mar 22 '15 at 10:36

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