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I have written a simple D-type flip flop using VHDL and am sythesizing it in Xilinx ISE. I wish to specify the setup and hold times. In my user constraints file I put the line:

TIMEGRP "D" OFFSET = IN 10 ns VALID 10 ns BEFORE "clk" RISING;

Am I right in thinking that this asks that the input D becomes valid a maximum 10ns before the rising clock edge, and must stay constant for a maximum 10ns? So in this case the setup time would be 10ns and the hold time would be 0ns?

Thanks.

epsilon_j
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  • Why do you want to change Setup and Hold times? They are already implemented by Xilinx and depend on the chosen hardware. – Paebbels Jan 29 '15 at 01:56
  • @Paebbels Then what is the purpose of the input constraints in the UCF? – epsilon_j Jan 29 '15 at 08:27
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    It's for the unknown world outside of an IC. E.g. a SRAM chip. If you specify setup and hold times for this chip, the STA can check if all timings from and to the chip are met. Otherwise it can only check timing inside the FPGA. – Paebbels Jan 29 '15 at 08:33

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