How to prevent ISE compiler from optmizing away my array?

Question

I'm new to Verilog, ISE, FPGAs. I'm trying to implement a simple design into an FPGA, but the entire design is being optimized away. It is basically an 2D array with some arbitrary values. Here is the code:

module top(
    output reg out
);

integer i;
integer j;
reg [5:0] array [0:99][0:31];

initial begin
    for(i=0;i<100;i=i+1) begin
            for(j=0;j<32;j=j+1) begin
                    array[i][j] = j;
                    out = array[i][j];
            end
    end
end

endmodule

It passes XST Synthesis fine, but it fails MAP in the Implementation process. Two Errors are given:

ERROR:Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.

The entire code is being optimized away in XST. Why? What am I doing wrong?

Unn · Accepted Answer · 2015-05-06T01:03:29.740

The reason your design is being synthesized away is because you have not described any logic in your module.

The only block in your design is an initial block which is typically not used in synthesis except in limited cases; the construct mainly used for testbenches in simulation (running the Verilog through ModelSim or another simluator).

What you want is to use always blocks or assign statements to describe logic for XST to synthesize into a netlist for the FPGA to emulate. As the module you provided has neither of these constructs, no netlist can be generated, thus nothing synthesized!

In your case, it is not entirely clear what logic you want to describe as the result of your module will always have out equal to 31. If you want out to cycle through the values 0 to 31, you'll need to add some sequential logic to implement that. Search around the net for some tutorials on digital design so you have the fundamentals down (combinational logic, gates, registers, etc). Then, think about what you want the design to do and map it to those components. Then, write the Verilog that describes that design.

EDIT IN LIGHT OF COMMENTS:

The reason you are get no LUT/FF usage on the report is because the FPGA doesn't need to use any resources (or none of those resources) to implement your module. As out is tied to constant 31, it will always have the value of 1, so the FPGA only needs to tie out to Vdd (NOTE that out is not 31 because it is only a 1-bit reg). The other array values are never used nor accesses, so the FPGA synthesized them away (ie, not output needs to know the value of array[0][1] as out is a constant and no other ports exist in the design). In order to preserve the array, you need only use it to drive some output somehow. Heres a basic example to show you:

module top( input [6:0] i_in, // Used to index the array like i
            input [4:0] j_in, // Used to index the array like j
            output reg [5:0] out // Note, out is now big enough to store all the bits in array
          );

  integer i;
  integer j;
  reg [5:0] array[0:99][0:31];

  always @(*) begin
    // Set up the array, not necessarily optimal, but it works
    for (i = 0; i < 100; i = i + 1) begin
      for (j = 0; j < 32; j = j + 1) begin
        array[i][j] = j;
      end
    end

    // Assign the output to value in the array at position i_in, j_in
    out = array[i_in][j_in];
  end

endmodule

If you connect the inputs i_in and j_in to switches or something and out to 6 LEDs, you should be able to index the array with the switches and get the output on the LEDs to confirm your design.

I agree, but... `initial` is totally supported in synthesis by XST (as long as the assigned value is a constant). For a register, it it the `INIT` value of the register, for a memory, it is it's initial content. It is very useful for ROM for instance. You can look up XST user guide for more details: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf — Jonathan Drolet, May 05 '15 at 00:32
Very true, which is why I said limited cases :) Though, you need another process in an `assign` or `always` to actual read from the ROM/RAM or register (The `initial` doesnt translate to any logic). As the OP is new to Verilog, I didnt want to go into that until he has the fundamentals down; but its a good thing to keep in mind. — Unn, May 05 '15 at 00:40
I changed that initial block for an always block and it got through synthesis and implementation. However, the design is still being totally optimized away. Any ideas on this? BTW I'll make sure I find a good Primer to get some fundamental Verilog — Luis Filipe Martins Barros, May 05 '15 at 01:24
It is optimized away because out has only one possible value. You need an input to have to be part of the function — Greg, May 05 '15 at 01:54
Yeah, that was it again. One last question: now everything is working properly, but my MAP report tells me no LUTs, FFs or anyting are being used. Only two ports (one in and one out). That makes sense? Anyway, is there a way to store each of the values of the array in the FPGA? In one or many regs, or something like that? Thanks for all the help btw — Luis Filipe Martins Barros, May 05 '15 at 20:42

How to prevent ISE compiler from optmizing away my array?

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