0

I have a 8192 row (13 bit address) and 12 bit width block ram. i write this 1
In Virtex-6, we have 36kb Block Rams. So ISE Design Suite implements my ram as three 36kb BRAM with 4 bit width.

For timing issues, I want ISE to use individual flip-flops for each BRAM read/write address. So for read/write address reg I set properties but they are not applied.
this is implemented
what i want

Community
  • 1
  • 1
Mohammad
  • 69
  • 10
  • You should make a module combining FF, with Dual Port RAM (having data bus = 4 bits) and instantiate that module 3 times in the upper module. – Karan Shah Mar 07 '16 at 14:08
  • I want ISE to do it automatically, because I want to use this module with different data width, I set data width via a parameter. – Mohammad Mar 09 '16 at 08:12

1 Answers1

0

A general solution to this kind of problem is to put in a separate layer of hierarchy anything you wish the synthesiser not to change. This then gives it a name (its instance name), to which you can then refer in your synthesiser in order to tell it not to change that part of the hierarchy.

So, in your case, you could put these the process that infers these flip-flops in a separate layer of hierarchy. I don't know how to tell ISE to then leave these layers of hierarchy alone, but I'm pretty sure there will be a way of doing it. (Now you know the general principle, you can search the manual just as well as I can).

Matthew Taylor
  • 13,365
  • 3
  • 17
  • 44