Questions tagged [system-generator]
14 questions
4
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1 answer
Matrix Multiplication of two Complex Vectors in Simulink
Two questions really, But I would like to make it more descriptive :
I am implementing a Modulator which involves Matrix Multiplication of complex Vector:
Just to give an example :
cck_encoding_table(1,:)= [ 1j 1 1j -1 1j 1 -1j 1…

Kiran
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2 answers
USRP2 Overflow problem
I am trying to capture the wlan samples from gnuradio-companion. I have configured the USRP Soource with the following :
Ch0 Gain = 50dB
device addr : 192.168.10.3
Center Frequency : 2.437GHz
Sample Rate : 11M
But , when I execute the model,…

Kiran
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1
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1 answer
Tool to Monitor Serial Port in USRP2
I am working on USRP2 and would like to read the debug messages. There is a serial port at the rear-end.
I connect a standard USB to 3.3v-level serial converter. But I am not sure, which tool to use to read the messages.
As per the specification, I…

Kiran
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1 answer
Problem with Parallel-to-Serial block in Simulink
I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream.
So I am using the Parallel-to-Serial Block of Xilinx Library in Simulink.
But I am not able to use the block, I get the following error…

Kiran
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1
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1 answer
How to obtain a absolute of a number in Xilinx Simulink?
I need to get the absolute of the signal in Xilinx Simulink.
I can use a mcode block and write matlab code to achieve it. But, just curious if there is a better way of doing it.
I am very new to using Simulink(Xilinx). Is there any abs block as in…

Kiran
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1 answer
fixpoint feature in MATLAB
when I am using simulink, the following warning appear to me
Warning: Support for ver('fixpoint') will be removed in a future release.
and the fixpoint feature is very important to my work (working with system generator)
Please, can anyone help me…

Serwan Bamerni
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1
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0 answers
hardware co simulation using Digilent Atlys FPGA is Slow
I'm using DIGILENT's Atlys FPGA board for image processing but i'm facing one problem that is when i do software co simulation using Black box i'm getting the output very soon i.e, within 1 min but when i generate hardware co simulation model and…

FPGA LORD
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1
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1 answer
System Generator configuration for Xilinx Co Simulation
I'm working on a cosimulation in simulink using either 2012a or 2011b, and System Generator 13.1. When building the library block for the hardware to be loaded onto the zynq fpga, I configure the system generator to be a 'Hardware Co-Sim,'…

alexharris
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0
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1 answer
Error during Netlist Generation in Simulink
I was trying to generate a netlist from a simple Model in simulink. I can run the simulation (using sysgen).
When I try to create a netlist , it throws an error :
"
* ERROR *
Errors occurred during netlist
generation. Error using ==>
…

Kiran
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0
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3 answers
Integer to Binary Conversion in Simulink
This might look a repetition to my earlier question. But I think its not.
I am looking for a technique to convert the signal in the Decimal format to binary format.
I intend to use the Simulink blocks in the Xilinx Library to convert decimal to…

Kiran
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0
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1 answer
Sequential instatiation of Verilog Modules
I am trying to implement an algorithm on hardware(ZedBoard) which has multiple modules. There is a top module and I will instantiate all these multiple modules inside the top module.
Approximately there are 9 to 10 modules of which 3 has to run…

Ganesh Prasad B K
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0
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1 answer
Configure clock signal for black box in Simulink/System Generator
I use code VHDL to make a one-shot timer in Simulink by "black box" of System Generator. The module concludes input is: clk, en, trigger, delay & output is: pluse. Now I want to use System Generator to implement on Zynq 7020 and use clock frequency…

Thanh niên Yên Bái
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0
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1 answer
Matlab System generator: error with black box
I using Xilinx system generator blocks in Matlab.
I simply using only a black box with a gateway in and gateway out.
The code for the black box is very simple and work correctly with ISE design suite
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use…

Serwan Bamerni
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0
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0 answers
Xilinx System Generator Pulse Compression
I am making a system generator model for radar pulse compression using HW Cosimulation of Spartan 6.
On internet there are three research papers which are close to what I want to find.
You can see the models in research paper.
Two are using FIR…

firefoot007
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