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I am trying to write a 1-bit comparator VHDL code in Xilinx ISE.

There are no errors in the code but when I tried to create a schematic symbol, this error has arisen:

ERROR: G:/eq/eq.sym was not updated. Set the 'Overwrite Existing Symbol' process property to enable overwritting of existing symbol files.

What can I do to fix this problem? 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity eq is
  port (
    i0 : in  STD_LOGIC;
    i1 : in  STD_LOGIC;
    eq : out STD_LOGIC);
end eq;

architecture sop_arch of eq is
  signal P0 , p1: std_logic;
begin
  eq <= P0 or p1;
  p0 <= ( not i0) and ( not i1);
  p1 <= i0 and i1;
end sop_arch;
Cactus
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maryam
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  • What about following the instructions in the error message? Btw `eq <= i0 xnor i1;` – Paebbels Apr 24 '16 at 17:35
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    Don't let @Paebbels distract you, your VHDL simulates just [fine](http://i.stack.imgur.com/Z3fo9.png). This isn't a VHDL problem, rather a tool issue. It isn't clear there's an error other than with a non VHDL standard compliant tool. The VHDL standard places the entity declaration and the port declaration for eq in two different declarative regions. One easy solution would be to change the name eq in one of the two declarations in your VHDL code. –  Apr 24 '16 at 22:27
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    I don't think the error is related to using the identifier `eq` twice. It's a problem with an already existing symbol (*.sym) file as the error message says. – Paebbels Apr 24 '16 at 23:17
  • So change it both places. –  Apr 25 '16 at 06:09
  • thank you all, I have fixed the problem and now I have a schematic. but unfortunately the program cant be synthesized!!! may be the problem is about the software. please introduce me a link to download the xilinx ISE software and install it again. I have windows 7 on my pc. – maryam Apr 25 '16 at 10:13

0 Answers0