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Now I am making a project relating to MGT (Multi-Gigabit Transceiver) GTP.

Because I am a newbie in verilog programming language, I have one question about the MGT GTP.

In the Xilinx document (Virtex-5 FPGA ROCKETIO GTP transceiver), TX sides (figure) has one FIFO-TX buffer (Phase adjust FiFo and Oversampling).

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From the information I read in this document, I understand that this module is only used to adjust the clock phase of TX side and minimize the skew of the GTP transceiver.

It is not difficult for me to generate one asynchronous or synchronous FIFO to connect to MGT GTP but it will increase the jitter latency.

I thought that if I can use TX buffer inside the MGT GTP, it is possible to reduce the jitter latency.

Therefore, my question is that

Could I use this TX buffer to transmit data as synchronous or asynchronous FIFO bram ?

If I can use this buffer as synchr and asynchr FIFO, are there the status flag (empty or full) for this TX buffer ?

Thank you so much

Tai Chau
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1 Answers1

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You cannot use it "as" a BRAM as it is an internal transceiver component. It's an internal asynchronous FIFO that bridges the TXUSERCLK domain to the XCLK domain, and nothing more. It looks like you can get a 'water mark' status signal out of the buffer via the TXBUFSTATUSn signal, but this is only a one-bit signal indicating more or less than half full, not a full or empty indication. And there is no way to indicate that data into the FIFO is valid or not, every cycle in the TXUSERCLK domain is considered valid data. The phase alignment/deskew routines seem to be the only thing that can actually change the amount of data in the buffer. Well, that and running TXUSERCLK at a different frequency than XCLK, but this will just result in buffer overflow or buffer underflow, necessitating a reset of the transmitter. The thing to note about the deskew routines is that they are designed to align the XCLK of two adjacent transmitter channels, not to minimize the delay through a single channel.

I have no idea what you mean by "jitter latency."

alex.forencich
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  • Thank you so much for your answer. It is very detailed and easy to understand the role of this FIFO in MGT. About the jitter latency, I misunderstood. It is just latency between write into and read out data from FIFO (example BRAM FIFO). I thought that if I skip this FIFO by using the FIFO inside the MGT, I will save more time inside the FPGA. – Tai Chau Jun 07 '18 at 09:20
  • How much time are you hoping to save? FIFO read and write latency is only going to be a clock cycle or two, not more than a handful of nanoseconds. That's not considering time spent sitting in the FIFO, but if you're serious about latency then you should be minimizing that anyway. – alex.forencich Jun 07 '18 at 19:57