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Now, I am making the protocol (Aurora-Xilinx) to connects two boards together. and I would like to check bit errors for transmit data and receive data. To check bit errors, transmit data on board 1 is looped back on board 2 and then come back board 1. Then I wrote own firmware for checking bit errors by comparing transmit data and receive data.

However, receive data always delays with transmit data by some clock cycles or many cycles. My idea is shifting the transmit data to the clock position which the first corresponding receive data begins to appear. If you look at the figure attached in this post, the red box is frame of transmit data and yellow box is corresponding receive data. But I would like to write the general firmware to resolve this delay. This means that with any delay , transmit data is always shifted to right clock position when the first corresponding receive data appears. I think that when I solve this problem, I can compare transmit and receive data together to get the bit error values.

If you have any open sample verilog code or suggestions for my problems, please let me know. Especially, if you have another ideas or detailed documents for checking bit errors, please let me know.

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Tai Chau
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Automatic detecting the length of the delay is a circuit which requires pattern hunting: Keeping a copy of the transmitted data and comparing with the received data shifting through N positions. Even that does not work with all possible patterns as you can easily have false positives.

Normally testing in loop back is done with know patterns or error detection like adding a CRC.

Oldfart
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